Alinx ZYNQ UltraScale+ User Manual
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Alinx ZYNQ UltraScale+ User Manual

Fpga development board
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ZYNQ UltraScale+
FPGA Development Board
AXU9EG
User Manual

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Summary of Contents for Alinx ZYNQ UltraScale+

  • Page 1 ZYNQ UltraScale+ FPGA Development Board AXU9EG User Manual...

  • Page 2: Version Record

    ZYNQ Ultrascale + FPGA Board AXU9EG User Manual Version Record Version Date Release By Description Rev 1.1 2021-07-21 Rachel Zhou First Release Amazon Store: https://www.amazon.com/alinx 2 / 66...

  • Page 3: Table Of Contents

    Part 3.8: SFP Interface................48 Part 3.9: CAN Communication Interface..........49 Part 3.10: 485 Communication Interface..........50 Part 3.11: MIPI Camera Interface.............51 Part 3.12: FMC Interface................52 Part 3.13: 40-Pin Expansion Headers............. 57 Part 3.14: JTAG Debug Port..............58 Amazon Store: https://www.amazon.com/alinx 3 / 66...
  • Page 4 Part 3.16: EEPROM and Temperature Sensor........60 Part 3.17: User LEDs..................61 Part 3.18: Keys.................... 62 Part 3.19: DIP Switch Configuration............62 Part 3.20: Power Supply................63 Part 3.21: ALINX Customized Fan............64 Part 3.22: Carrier Board Size Dimension..........66 Amazon Store: https://www.amazon.com/alinx 4 / 66...
  • Page 5 It is a "professional" ZYNQ development platform. For high-speed data transmission and exchange, pre-verification and post-application of data processing is possible. This product is very suitable for students, engineers and other groups engaged in MPSoCs development. Amazon Store: https://www.amazon.com/alinx 5 / 66...
  • Page 6 ZYNQ Ultrascale + FPGA Board AXU9EG User Manual Amazon Store: https://www.amazon.com/alinx 6 / 66...

  • Page 7: Part 1: Fpga Development Board Introduction

    2 SFP Interfaces, 2 SATA Interfaces, 2 UART, 1 SD card slot, 1 FMC Interface, 2-Channel CAN bus interfaces, 2-Channel RS485 bus interfaces, 1 MIPI Camera Interface, 40-pin expansion ports and some keys and LEDs. The following figure shows the structure of the entire development system: Amazon Store: https://www.amazon.com/alinx 7 / 66...
  • Page 8 PS system, and a differential 200MHz crystal oscillator for the PL logic DDR reference clock.  M.2 Interface 1 PCIEx1 standard M.2 interface, used to connect M.2 SSD solid state drives, with a communication speed of up to 6Gbps.  DP Output Interface Amazon Store: https://www.amazon.com/alinx 8 / 66...
  • Page 9  FMC Expansion Interface 1 standard FMC LPC expansion port, which can be connected to various FMC modules of XILINX or ALINX (HDMI input and output modules, binocular camera modules, high-speed AD modules, etc.).  CAN Communication Interface Amazon Store: https://www.amazon.com/alinx...
  • Page 10 2 Lane MIPI camera input interfaces, used to connect MIPI camera module (AN5641).  40-pin Expansion Header The 40-pin 2.54mm pitch expansion port use for external ALINX modules (binocular camera, TFT LCD screen, high-speed AD module, etc.). The expansion port includes 1 channel of 5V power supply, 2 channels of 3.3V power supply, 3 channels of ground, and 34 channels...
  • Page 11 ZYNQ Ultrascale + FPGA Board AXU9EG User Manual indicator,1 DONE Configuration indicator and 2 user indicators on the carrier board.  KEYs 3 KEYs, include 1 Rest KEY and 2 User KEYs. Amazon Store: https://www.amazon.com/alinx 11 / 66...

  • Page 12: Part 2: Acu9Eg Core Board

    IO ports on the PL side (HP I/O: 96, HD I/O: 84). The wiring between the XCZU9EG chip and the interface has been processed with equal length and differential, and the core board size is only 3.15*2.36 (inch), which is very suitable for secondary development. Amazon Store: https://www.amazon.com/alinx 12 / 66...

  • Page 13: Part 2.2: Zynq Chip

    Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end contains a wealth of programmable logic units, DSP and internal RAM. . Figure 2-2-1 detailed the Overall Block Diagram of the ZU9EG Chip. Amazon Store: https://www.amazon.com/alinx 13 / 66...
  • Page 14  External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3 interface  Static storage interface, support NAND, 2xQuad-SPI FLASH.  High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0, Sata 3.1, Display Port, 4 x Tri-mode, Gigabit Ethernet Amazon Store: https://www.amazon.com/alinx 14 / 66...

  • Page 15: Part 2.3: Ddr4 Dram

    2GB. The maximum operating speed of the DDR4 SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems are directly connected to the memory interface of the PS BANK504. The Amazon Store: https://www.amazon.com/alinx 15 / 66...
  • Page 16 The hardware connection of DDR4 SDRAM on the PS Side is shown in Figure 2-3-1: Figure 2-3-1: DDR3 DRAM schematic diagram The hardware connection of DDR4 SDRAM on the Pl Side is shown in Figure 2-3-2: Amazon Store: https://www.amazon.com/alinx 16 / 66...
  • Page 17 AH23 PS_DDR4_DQS3_P PS_DDR_DQS_P3_504 AH22 PS_DDR4_DQS4_N PS_DDR_DQS_N4_504 AH29 PS_DDR4_DQS4_P PS_DDR_DQS_P4_504 AH28 PS_DDR4_DQS5_N PS_DDR_DQS_N5_504 AE29 PS_DDR4_DQS5_P PS_DDR_DQS_P5_504 AE28 PS_DDR4_DQS6_N PS_DDR_DQS_N6_504 AK32 PS_DDR4_DQS6_P PS_DDR_DQS_P6_504 AJ32 PS_DDR4_DQS7_N PS_DDR_DQS_N7_504 AE33 PS_DDR4_DQS7_P PS_DDR_DQS_P7_504 AE32 PS_DDR4_DQ0 PS_DDR_DQ0_504 AP20 PS_DDR4_DQ1 PS_DDR_DQ1_504 AP18 Amazon Store: https://www.amazon.com/alinx 17 / 66...
  • Page 18 AG24 PS_DDR4_DQ27 PS_DDR_DQ27_504 AG23 PS_DDR4_DQ28 PS_DDR_DQ28_504 AK22 PS_DDR4_DQ29 PS_DDR_DQ29_504 AJ21 PS_DDR4_DQ30 PS_DDR_DQ30_504 AJ22 PS_DDR4_DQ31 PS_DDR_DQ31_504 AK23 PS_DDR4_DQ32 PS_DDR_DQ32_504 AG31 PS_DDR4_DQ33 PS_DDR_DQ33_504 AG30 PS_DDR4_DQ34 PS_DDR_DQ34_504 AG29 PS_DDR4_DQ35 PS_DDR_DQ35_504 AG28 PS_DDR4_DQ36 PS_DDR_DQ36_504 AJ30 PS_DDR4_DQ37 PS_DDR_DQ37_504 AK29 Amazon Store: https://www.amazon.com/alinx 18 / 66...
  • Page 19 AD34 PS_DDR4_DQ63 PS_DDR_DQ63_504 AD33 PS_DDR4_DM0 PS_DDR_DM0_504 AG20 PS_DDR4_DM1 PS_DDR_DM0_504 AN17 PS_DDR4_DM2 PS_DDR_DM1_504 AM21 PS_DDR4_DM3 PS_DDR_DM2_504 AK19 PS_DDR4_DM4 PS_DDR_DM3_504 AH24 PS_DDR4_DM5 PS_DDR_DM4_504 AH31 PS_DDR4_DM6 PS_DDR_DM5_504 AE30 PS_DDR4_DM7 PS_DDR_DM6_504 AJ31 PS_DDR4_A0 PS_DDR_A0_504 AP29 PS_DDR4_A1 PS_DDR_A1_504 AP30 Amazon Store: https://www.amazon.com/alinx 19 / 66...
  • Page 20 PS_DDR4_RESET_B PS_DDR_RST_N_504 AF21 PS_DDR4_CLK0_P PS_DDR_CK0_504 AN26 PS_DDR4_CLK0_N PS_DDR_CK_N0_504 AN27 PS_DDR4_CKE0 PS_DDR_CKE0_504 AN29 PL Side DDR4 DRAM pin assignment: Signal Name Pin Name Pin Number PL_DDR4_DQS0_N IO_L22N_T3U_N7_DBC_AD0N_65 PL_DDR4_DQS0_P IO_L22P_T3U_N6_DBC_AD0P_65 PL_DDR4_DQS1_N IO_L16N_T2U_N7_QBC_AD3N_65 PL_DDR4_DQS1_P IO_L16P_T2U_N6_QBC_AD3P_65 PL_DDR4_DQS2_N IO_L10N_T1U_N7_QBC_AD4N_65 Amazon Store: https://www.amazon.com/alinx 20 / 66...
  • Page 21 PL_DDR4_DQ19 IO_L12N_T1U_N11_GC_65 PL_DDR4_DQ20 IO_L9P_T1L_N4_AD12P_65 PL_DDR4_DQ21 IO_L8N_T1L_N3_AD5N_65 PL_DDR4_DQ22 IO_L12P_T1U_N10_GC_65 PL_DDR4_DQ23 IO_L11N_T1U_N9_GC_65 PL_DDR4_DQ24 IO_L3P_T0L_N4_AD15P_65 AE12 PL_DDR4_DQ25 IO_L5N_T0U_N9_AD14N_65 PL_DDR4_DQ26 IO_L2N_T0L_N3_65 AH11 PL_DDR4_DQ27 IO_L6N_T0U_N11_AD6N_65 PL_DDR4_DQ28 IO_L2P_T0L_N2_65 AH12 PL_DDR4_DQ29 IO_L5P_T0U_N8_AD14P_65 AG10 PL_DDR4_DQ30 IO_L3N_T0L_N5_AD15N_65 AF12 PL_DDR4_DQ31 IO_L6P_T0U_N10_AD6P_65 AD10 PL_DDR4_DM0 IO_L19P_T3L_N0_DBC_AD9P_65 Amazon Store: https://www.amazon.com/alinx 21 / 66...

  • Page 22: Part 2.4: Qspi Flash

    The FPGA core board ACU9EG is equipped with two 256MBit Quad-SPI FLASH chip to form an 8-bit bandwidth data bus, the flash model is MT25QU256ABA1EW9, which uses the 1.8V CMOS voltage standard. Due to Amazon Store: https://www.amazon.com/alinx 22 / 66...
  • Page 23 PS ports need to be configured as the QSPI FLASH interface. Figure 2-4-1 shows the QSPI Flash in the schematic. Figure 2-4-1: QSPI Flash in the schematic Configure chip pin assignments: Signal Name Pin Name Pin Number MIO5_QSPI0_SS_B PS_MIO5_500 AM15 Amazon Store: https://www.amazon.com/alinx 23 / 66...

  • Page 24: Part 2.5: Emmc Flash

    PS part of the ZYNQ UltraScale+. In the system design, it is necessary to configure the GPIO port function of the PS side as an EMMC interface. Figure 2-5-1 shows the part of eMMC Flash in the schematic diagram. Amazon Store: https://www.amazon.com/alinx 24 / 66...

  • Page 25: Part 2.6: Clock Configuration

    The core board provides reference clock and RTC real-time clock for PS system and PL logic respectively, so that PS system and PL logic can work independently. The schematic diagram of the clock circuit design is shown in Figure 2-6-1: Amazon Store: https://www.amazon.com/alinx 25 / 66...
  • Page 26 PS system. The crystal is connected to the PS_PADI_503 and PS_PADO_503 pins of BANK503 of the ZYNQ chip. The schematic diagram is shown in Figure 2-6-2: Figure 2-6-2: Passive Crystal Oscillator for RTC Clock pin assignment: Signal Name PS_PADI_503 PS_PADO_503 Amazon Store: https://www.amazon.com/alinx 26 / 66...
  • Page 27 (MRCC) of PL BANK64. This global clock can be used to drive the DDR4 controller and user logic circuits in the FPGA. The schematic diagram of this clock source is shown in Figure 2-6-4 Amazon Store: https://www.amazon.com/alinx 27 / 66...

  • Page 28: Part 2.7: Power Supply

    XCZU9EG chip. For the TPS6508640 power supply design, please refer to the power supply chip manual. The design block diagram is as follows : Amazon Store: https://www.amazon.com/alinx 28 / 66...
  • Page 29 ZYNQ Ultrascale + FPGA Board AXU9EG User Manual Amazon Store: https://www.amazon.com/alinx 29 / 66...

  • Page 30: Part 2.8: Acu9Eg Core Board Size Dimension

    BANK66, 67 is determined by the VCCO_66 and VCCO_67 power supply of the carrier board, the carrier board provides +1.8V by default. Pin assignment of board to board connector J29 Amazon Store: https://www.amazon.com/alinx 30 / 66...
  • Page 31 B67_L16_P B67_L6_P B67_L16_N B67_L6_N B67_L19_N B66_L14_N B67_L19_P B66_L14_P B66_L9_P B66_L21_P B66_L9_N B66_L21_N B67_L8_P B67_L21_N B67_L8_N B67_L21_P B67_L5_P B67_L24_N B67_L5_N B67_L24_P B66_L22_N B66_L13_P B66_L22_P B66_L13_N B66_L24_N B67_L4_P B66_L24_P B67_L4_N B67_L20_P B67_L22_P B67_L20_N B67_L22_N B67_L23_N B67_L17_P Amazon Store: https://www.amazon.com/alinx 31 / 66...
  • Page 32 J30 is connected to the transceiver signal of BANK505 MGT, MIO of PS, VCCO_66, VCCO_67 and +12V power supply. The MIO level of PS is 1.8V standard J29 Pin Signal Name J29 Pin Signal Name Number Number 505_TX0_P AB29 505_CLK0_P AA27 505_TX0_N AB30 505_CLK0_N AA28 Amazon Store: https://www.amazon.com/alinx 32 / 66...
  • Page 33 505_CLK3_N 505_TX1_P PS_MIO26 USB_STP PS_MIO35 USB_DIR PS_MIO28 USB_CLK PS_MIO37 USB_NXT PS_MIO39 USB_DATA0 PS_MIO27 USB_DATA1 PS_MIO40 USB_DATA2 PS_MIO30 USB_DATA3 PS_MIO34 USB_DATA4 PS_MIO29 USB_DATA5 PS_MIO31 USB_DATA6 PS_MIO32 USB_DATA7 PS_MIO42 PHY1_MDC PS_MIO36 PHY1_MDIO PS_MIO33 PHY1_TXD0 PS_MIO38 PHY1_TXD1 Amazon Store: https://www.amazon.com/alinx 33 / 66...
  • Page 34 BANK66, 67 is determined by the VCCO_66 and VCCO_67 power supply of the carrier board, the carrier board provides +1.8V by default. J31 Pin Signal Name J31 Pin Signal Name Number Number FPGA_TCK POWER_SW FPGA_TMS PS_MODE3 FPGA_TDO PS_MODE2 FPGA_TDI Amazon Store: https://www.amazon.com/alinx 34 / 66...
  • Page 35 B44_L6_N AL12 B44_L1_N AP14 B44_L2_N AN13 B44_L1_P AN14 B44_L2_P AM14 B44_L3_N AP12 B44_L3_P AN12 B44_L4_N AM13 B44_L4_P AL13 B44_L10_P AG14 B44_L10_N AG13 B50_L8_N B44_L9_N AF13 B50_L8_P B44_L9_P AE13 B50_L7_N B50_L6_P B50_L7_P B50_L6_N B50_L5_N B50_L5_P Amazon Store: https://www.amazon.com/alinx 35 / 66...
  • Page 36 J32 connects the IO of BANK47, 48, 49 and the transceiver signal of BANK128, 129, 130. J32 Pin Signal Name Pin Number J32 Pin Signal Name Pin Number B48_L5_P B48_L10_N B48_L5_N B48_L10_P B48_L11_P B49_L9_N B48_L11_N B49_L9_P B49_L8_N B47_L12_N B49_L8_P B47_L12_P B47_L11_N B49_L4_N B47_L11_P B49_L4_P Amazon Store: https://www.amazon.com/alinx 36 / 66...
  • Page 37 130_TX3_P 130_RX2_P 130_RX0_N 130_RX1_N 130_RX0_P 130_RX1_P 130_TX0_N 130_TX1_N 130_TX0_P 130_TX1_P 130_CLK0_N 130_CLK1_N 130_CLK0_P 130_CLK1_P 129_TX3_N 129_RX3_N 129_TX3_P 129_RX3_P 129_RX1_N 129_TX2_N 129_RX1_P 129_TX2_P 129_TX1_N 129_RX2_N 129_TX1_P 129_RX2_P 129_RX0_N 129_TX0_N 129_RX0_P 129_TX0_P 129_CLK0_N 129_CLK1_N 129_CLK0_P 129_CLK1_P Amazon Store: https://www.amazon.com/alinx 37 / 66...
  • Page 38 ZYNQ Ultrascale + FPGA Board AXU9EG User Manual 128_TX3_N 128_RX3_N 128_TX3_P 128_RX3_P 128_TX2_N 128_RX1_P 128_TX2_P 128_RX1_N 128_TX0_N 128_RX0_P 128_TX0_P 128_RX0_N 128_TX1_N 128_RX2_P 128_TX1_P 128_RX2_N 128_CLK0_N 128_CLK1_P 128_CLK0_P 128_CLK1_N Amazon Store: https://www.amazon.com/alinx 38 / 66...

  • Page 39: Part 3: Carrier Board

    6Gbps. The M.2 interface uses the M key slot, which only supports PCI-E, not SATA. When users choose SSD solid state drives, they need to choose PCIE type SSD solid state drives. Amazon Store: https://www.amazon.com/alinx 39 / 66...

  • Page 40: Part 3.3: Dp Interface

    AA28 PCIE Reference Clock Negative PCIE_RSTn_MIO37 PS_MIO37 PCIE Reset Signal Part 3.3: DP Interface The AXU15EG FPGA development board has a standard DisplayPort output display interface for video image display. The interface supports VESA Amazon Store: https://www.amazon.com/alinx 40 / 66...
  • Page 41 Transmit Positive Low bits of DP Data GT0_DP_TX_N 505_TX3_N Transmit Negative High bits of DP Data GT1_DP_TX_P 505_TX2_P Transmit Positive High bits of DP Data GT1_DP_TX_N 505_TX2_N Transmit Negative DP Reference Clock 505_DP_CLKP 505_CLK2_P Positive Amazon Store: https://www.amazon.com/alinx 41 / 66...

  • Page 42: Part 3.4: Usb3.0 Interface

    USB Slave peripherals (such as USB mouse, keyboard or U disk) at the same time. The schematic diagram of USB3.0 connection is shown as 3-4-1: Figure 3-4-1: USB3.0 Interface Schematic Amazon Store: https://www.amazon.com/alinx 42 / 66...

  • Page 43: Part 3.5: Gigabit Ethernet Interface

    When the KSZ9031RNX is powered on, it will detect the level status of some specific IOs to determine its own operating mode. Table 3-5-1 describes the default settings after the GPHY chip is powered on. Amazon Store: https://www.amazon.com/alinx 43 / 66...
  • Page 44 ZYNQ and PHY chip KSZ9031RNX is communicated through RMII bus, and the transmission clock is 25Mhz. Data is sampled on the rising edge and falling samples of the clock. Figure 3-5-1: ZYNQ PS system and GPHY connection diagram Amazon Store: https://www.amazon.com/alinx 44 / 66...
  • Page 45 PHY2_RXD3 B66_L6_P Ethernet 2 Receive Data Bit3 PHY2_RXCTL B66_L12_N Ethernet 2 Receive Enable Signal PHY2_MDC B67_L15_P Ethernet 2 MDIO Clock Management PHY2_MDIO B67_L15_N Ethernet 2 MDIO Management Data PHY2_RESET B67_L11_N Ethernet 2 Reset Signal Amazon Store: https://www.amazon.com/alinx 45 / 66...

  • Page 46: Part 3.6: Usb To Serial Port

    USB to serial port ZYNQ pin assignment: Signal name Pin Name Pin Number Description PS_UART_TX PS_MIO43 PS Uart Data Output PS_UART_RX PS_MIO42 PS Uart Data Input PL_UART_TX B50_L4_P PL Uart Data Output PL_UART_RX B50_L4_N PL Uart Data Input Amazon Store: https://www.amazon.com/alinx 46 / 66...

  • Page 47: Part 3.7: Sd Card Slot Interface

    Pin Number Description SD_CMD SD_CMD SD Clock Signal SD_CD SD_CD SD Command Signal SD_D0 SD_D0 SD Data0 SD_D1 SD_D1 SD Data1 SD_D2 SD_D2 SD Data2 SD_D3 SD_D3 SD Data3 SD_CMD SD_CMD SD card insertion signal Amazon Store: https://www.amazon.com/alinx 47 / 66...

  • Page 48: Part 3.8: Sfp Interface

    Description Number SFP1_TX_N 228_TX2_N Optical Module 1 Data Transmit Negative SFP1_TX_P 228_TX2_P Optical Module 1 Data Transmit Positive SFP1_RX_N 228_RX2_N Optical Module 1 Data Receive Negative SFP1_RX_P 228_RX2_P Optical Module 1 Data Receive Positive Amazon Store: https://www.amazon.com/alinx 48 / 66...

  • Page 49: Part 3.9: Can Communication Interface

    The CAN transceiver chip selected TI's SN65HVD232C chip for user CAN communication services. The connection of the CAN transceiver chip on the PS side is show as Figure 3-9-1 Figure 3-9-1: Connection diagram of CAN transceiver chip on PS side Amazon Store: https://www.amazon.com/alinx 49 / 66...

  • Page 50: Part 3.10: 485 Communication Interface

    The 485 communication pins are assigned as follows: Signal Name Pin Name Pin Number Description PL_485_TXD1 B44_L10_N AG13 The 1 Channel 485 Transceiver PL_485_RXD1 B44_L4_P AL13 The 1 Channel 485 Receiver PL_485_DE1 B44_L10_P AG14 The 1 Channel 485 Transmit Enable Amazon Store: https://www.amazon.com/alinx 50 / 66...

  • Page 51: Part 3.11: Mipi Camera Interface

    Part 3.11: MIPI Camera Interface The AXU15EG carrier board includes a MIPI camera interface, which can be used to connect with the ALINX Brand MIPI OV5640 camera module AN5641. MIPI interface 15PIN FPC connector, 2 LANE data and 1 pair of clock, connected to the differential IO pin of BANK67, other control signals are connected to the IO of BANK43, level standard It is 3.3V.

  • Page 52: Part 3.12: Fmc Interface

    Part 3.12: FMC Interface The AXU15EG FPGA Carrier board has a standard FMC HPC expansion port that can be connected to various FMC modules of XILINX or ALINX (HDMI input and output modules, binocular camera modules, high-speed AD modules, etc.). The FMC expansion port contains 36 pairs of differential IO signals and 8 pairs of GTX Transceivers.
  • Page 53 130_TX0_P Positive FMC Transceiver Data Transmission 0 FMC_DP0_C2M_N 130_TX0_N Negative FMC Transceiver Data Transmission 1 FMC_DP1_C2M_P 130_TX1_P Positive FMC Transceiver Data Transmission 1 FMC_DP1_C2M_N 130_TX1_N Negative FMC Transceiver Data Transmission 2 FMC_DP2_C2M_P 130_TX2_P Positive Amazon Store: https://www.amazon.com/alinx 53 / 66...
  • Page 54 FMC_DP1_M2C_N 130_RX1_N Negative FMC Transceiver Data Receive 2 FMC_DP2_M2C_N 130_RX2_N Positive FMC Transceiver Data Receive 2 FMC_DP2_M2C_P 130_RX2_P Negative FMC Transceiver Data Receive 3 FMC_DP3_M2C_P 130_RX3_P Positive FMC_DP3_M2C_N 130_RX3_N FMC Transceiver Data Receive 3 Amazon Store: https://www.amazon.com/alinx 54 / 66...
  • Page 55 B67_L22_P FMC Reference 5 Data P FMC_LA05_N B67_L22_N FMC Reference 5 Data N FMC_LA06_P B67_L17_P FMC Reference 6 Data P FMC_LA06_N B67_L17_N FMC Reference 6 Data N FMC_LA07_P B67_L8_P FMC Reference 7 Data P Amazon Store: https://www.amazon.com/alinx 55 / 66...
  • Page 56 B66_L24_P FMC Reference 23 Data P FMC_LA23_N B66_L24_N FMC Reference 23 Data N FMC_LA24_P B66_L8_P FMC Reference 24 Data P FMC_LA24_N B66_L8_N FMC Reference 24 Data N FMC_LA25_P B66_L5_P FMC Reference 25 Data P Amazon Store: https://www.amazon.com/alinx 56 / 66...

  • Page 57: Part 3.13: 40-Pin Expansion Headers

    Part 3.13: 40-Pin Expansion Headers The carrier board is reserved with one 0.1inch spacing standard 40-pin expansion ports J50, which is used to connect the ALINX modules or the external circuit designed by the user. The expansion port has 40 signals, of which 1-channel 5V power supply, 2-channel 3.3 V power supply, 3-channle...

  • Page 58: Part 3.14: Jtag Debug Port

    ZYNQ UltraScale+ chip by plugging and unplugging under power, we aded a protection diode to the JTAG signal to ensure that the signal voltage is within the range accepted by the FPGA and avoid damage to the ZYNQ UltraScale+ chip. Amazon Store: https://www.amazon.com/alinx 58 / 66...

  • Page 59: Part 3.15: Real-Time Clock

    The BT1 on the development board is a battery Socket. After we put the coin battery, even the system is off, the coin battery can also power the RTC system and provide continuous time information. Amazon Store: https://www.amazon.com/alinx 59 / 66...

  • Page 60: Part 3.16: Eeprom And Temperature Sensor

    The EEPROM and temperature sensor are mounted on the Bank500 MIO of ZYNQ UltraScale+ through the I2C bus. Figure 3-16-1 is the schematic diagram of EEPROM and temperature sensor Figure 3-16-1: EEPROM and Sensor connection diagram Amazon Store: https://www.amazon.com/alinx 60 / 66...

  • Page 61: Part 3.17: User Leds

    Pin assignment of user LED lights Signal Name ZYNQ Pin Name ZYNQ Pin Number Description PS_LED PS_MIO44 PS User LED Light PL_LED1 B44_L4_N AM13 PL User LED1 Light PL_LED2 B44_L3_N AP12 PL User LED2 Light Amazon Store: https://www.amazon.com/alinx 61 / 66...

  • Page 62: Part 3.18: Keys

    ZYNQ system. The AXU15EG system development platform supports 4 startup modes. The 4 startup modes are JTAG debug mode, QSPI FLASH, EMMC and SD2.0 card startup mode. After Amazon Store: https://www.amazon.com/alinx 62 / 66...

  • Page 63: Part 3.20: Power Supply

    DC12V is converted into +5V, +3.3V, +1.8V, and +1.2V, through one-way DC/DC power chip TPS54620 and three-way DC/DC power chip MP1482. The schematic diagram of the power supply design on the board is shown in Figure 3-20-1: Amazon Store: https://www.amazon.com/alinx 63 / 66...

  • Page 64: Part 3.21: Alinx Customized Fan

    Ethernet, USB2.0, SD, DP, CAN, RS485 +1.2V Ethernet Part 3.21: ALINX Customized Fan Because ZU9EG generates a lot of heat when it works normally, we add a heat sink and fan to the chip on the board to prevent the chip from overheating.
  • Page 65 The fan has been screwed to the FPGA development board before leaving the factory. The power of the fan is connected to the socket of J55. The red is positive and the black is negative. Amazon Store: https://www.amazon.com/alinx 65 / 66...

  • Page 66: Part 3.22: Carrier Board Size Dimension

    ZYNQ Ultrascale + FPGA Board AXU9EG User Manual Part 3.22: Carrier Board Size Dimension Figure 3-22-1: Top View Amazon Store: https://www.amazon.com/alinx 66 / 66...

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