Part 3.12: Fmc Interface - Alinx ZYNQ UltraScale+ User Manual

MIPI interface pin assignment
Signal Name
MIPI_CLK_P
MIPI_CLK_N
MIPI_LAN0_P
MIPI_LAN0_N
MIPI_LAN1_P
MIPI_LAN1_N
CAM_GPIO
CAM_CLK
CAM_SCL
CAM_SDA

Part 3.12: FMC Interface

The AXU15EG FPGA Carrier board has a standard FMC HPC expansion
port that can be connected to various FMC modules of XILINX or ALINX (HDMI
input and output modules, binocular camera modules, high-speed AD modules,
etc.). The FMC expansion port contains 36 pairs of differential IO signals and 8
pairs of GTX Transceivers.
The 36 pairs of differential signals of the FMC expansion port are
connected to the IO of the BANK66 and BANK67 of the ZYNQ Ultrascale+ chip.
The level standard is 1.8V, and the differential signal supports LVDS data
communication, 8 pairs of GTX transceiver signals are connected to BANK129
and BANK130. The schematic diagram of ZYNQ Ultrascale+ and FMC
connectors is shown in Figure 3-12-1.
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ZYNQ Ultrascale + FPGA Board AXU9EG User Manual
ZYNQ Pin Name
B67_L1_P
B67_L1_N
B67_L2_P
B67_L2_N
B67_L3_P
B67_L3_N
B44_L6_P
B44_L6_N
B44_L2_N
B44_L2_P
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ZYNQ Pin
Number
W12 MIPI Input Clock Positive
W11 MIPI Input Clock Negative
T13 MIPI Input Date LANE0 Positive
R13 MIPI Input Date LANE0 Negative
U10 MIPI Input Date LANE1 Positive
T10 MIPI Input Date LANE1 Negative
AK13 GPIO Control of Camera
AL12
AN13
AM14
Description
Clock Input of Camera
I2C Clock of Camera
I2C Data of Camera