Part 3.14: Jtag Debug Port - Alinx ZYNQ UltraScale+ User Manual

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

Part 3.14: JTAG Debug Port

The JTAG interface is reserved on the AXU15EG expansion board for
downloading ZYNQ UltraScale+ programs or firmware programs to FLASH. In
order to not damage the ZYNQ UltraScale+ chip by plugging and unplugging
under power, we aded a protection diode to the JTAG signal to ensure that the
signal voltage is within the range accepted by the FPGA and avoid damage to
the ZYNQ UltraScale+ chip.
58 / 66
ZYNQ Ultrascale + FPGA Board AXU9EG User Manual
IO_1N G19
IO_2N B19
IO_3N C19
IO_4N A12
IO_5N B13
IO_6N A20
IO_7N A15
IO_8N A22
IO_9N B12
IO_10N AG15
IO_11N AE14
IO_12N G14
IO_13N AK14
IO_14N AH13
IO_15N AP14
IO_16N G16
IO_17N J15
GND -
+3.3V -
Amazon Store: https://www.amazon.com/alinx
4 IO_1P
6 IO_2P
8 IO_3P
10 IO_4P
12 IO_5P
14 IO_6P
16 IO_7P
18 IO_8P
20 IO_9P
22 IO_10P
24 IO_11P
26 IO_12P
28 IO_13P
30 IO_14P
32 IO_15P
34 IO_16P
36 IO_17P
38 GND
40 +3.3V
G18
B18
C18
A13
C13
B20
B15
A21
C12
AF15
AE15
G15
AK15
AH14
AN14
H16
J16
-
-