Alinx ZYNQ7000 FPGA User Manual
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Alinx ZYNQ7000 FPGA User Manual

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ZYNQ7000 FPGA
Development Board
AC7010/AC7020
User Manual

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Summary of Contents for Alinx ZYNQ7000 FPGA

  • Page 1 ZYNQ7000 FPGA Development Board AC7010/AC7020 User Manual...

  • Page 2: Version Record

    ZYNQ FPGA Development Board AC7010/AC7020 User Manual Version Record Revision Date Release By Description Rev 1.0 2019-10-01 Rachel Zhou First Release 2 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 3: Table Of Contents

    Part 6.8: Reset Key ................30 Part 7：ZYNQ PL Peripherals ..............31 Part 7.1: User LEDs ................31 Part 7.2: Expansion Port J10 ............. 32 Part 7.3: Expansion Port J11 ............. 35 Part 7.4: Expansion Port J12 ............. 37 3 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 4 ZYNQ FPGA Development Board AC7010/AC7020 User Manual The two core boards of the ALINX XILINX ZYNQ7000 development platform were officially released in 2017, models: AC7010 and AC7020 (industrial grade). Their development platform is the solution for XILINX's Zynq7000 SOC chip. It uses ARM+FPGA SOC technology to integrate dual-core ARM Cortex-A9 and FPGA programmable logic on a single chip.

  • Page 5: Part 1: Introduction

    In addition, there is a 7 x 2 JTAG connector on the core board that can be downloaded and debugged via the ALINX Xilinx USB Cable Downloader. Figure 1-2 shows the structure of the entire AC7010/AC7020 system:...
  • Page 6  USB Uart Interface 1-channel USB Uart interface for serial communication with PC or external devices  LED Light 2 LEDs, 1 PS control LED, 1 PL control LED.  Key 1 reset button for CPU reset 6 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 7: Part 2: Dimensional Structure

     3-way 40-pin expansion port (0.1inch Spacing) 3-way 40-pin 0.1inch spacing expansion port for extending the IOs of ZYNQ PL and PL parts, and can be connect to various ALINX modules (binocular camera, TFT LCD screen, high-speed AD module, etc.) ...

  • Page 8: Part 3: Power Supply

    Please do not use other specifications of the power supply to avoid damage to the core board. The power supply design on the core board is as follows: Figure 3-1: Power Supply Schematic The development board is powered by +5V, and is converted into +1.5V, 8 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 9 ZYQN. The power-on sequence is +1.0V->+1.8V->+1.5 V-> (3.3V, VCCIO34, VCCIO35). Figure 3-2 shows the circuit design of the power supply: 9 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 10: Part 4: Zynq Chip

    Ethernet interface, SD/SDIO interface, I2C bus interface, CAN bus interface, UART interface, GPIO etc. The PS can operate independently and start up at power up or reset. Figure 4-1 detailed the Overall Block Diagram of the ZYNQ7000 Chip. 10 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 11  2 SPIs, 2 UARTs, 2 I2C interfaces  4 sets of 32bit GPIO, 54 (32+22) as PS system IO, 64 connected to PL  High bandwidth connection within PS and PS to PL 11 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 12 BGA. letter + Figure 4-2 detailed the XC7Z010 chip on the Core Board AC7010. Figure 4-2: The XC7Z010 chip on the Core Board AC7010 12 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 13: Part 4.1: Jtag Interface

    First, let's talk about the JTAG debug interface (J14) of the AC7010/AC7020 core board. Users can debug and download the ZYNQ program by connecting the ALINX Xilinx USB Cable downloader. Figure 4-3 shows the schematic part of the JTAG port, which involves four signals, TCK, TMS, TDO, and TDI.

  • Page 14: Part 4.3: Zynq Boot Configuration

    The order of power outages is reversed. Part 4.3: ZYNQ boot configuration The AC7010/AC7020 FPGA Core board supports three boot modes. The three boot modes are JTAG debug mode, QSPI FLASH and SD card boot 14 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 15: Part 5: Clock Configuration

    X1 crystal on the FPGA core board. The input of the clock is connected to the pin of the PS_CLK_500 of the BANK500 of the ZYNQ chip. The schematic diagram is shown in Figure 5-1: Figure 5-1: Active crystal oscillator to the PS section 15 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 16: Part 5.2: Pl System Clock Source

    FPGA. The schematic diagram of the clock source is shown in Figure 5-3. Figure 5-3: PL system clock source PL Clock pin assignment: Signal Name ZYNQ Pin 500_CLK 16 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 17: Part 6：Zynq Processor System (Ps) Peripherals

    ZYNQ chip. In the system design, the GPIO port functions of these PS ports need to be configured as the QSPI FLASH interface. Figure 6-1 shows the QSPI Flash in the schematic. 17 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 18 ZYNQ FPGA Development Board AC7010/AC7020 User Manual Figure 6-1: QSPI Flash Connection Diagram Figure 6-2: QSPI Flash on AC7010/AC7020 FPGA Core Board 18 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 19: Part 6.2: Ddr3 Dram

    The hardware design of DDR3 requires strict consideration of signal integrity. We have fully considered the matching resistor/terminal resistance, trace impedance control, and trace length control in circuit design and PCB design to ensure high-speed and stable operation of DDR3. 19 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 20 ZYNQ FPGA Development Board AC7010/AC7020 User Manual Figure 6-2: The Schematic Part of DDR3 DRAM Figure 6-3: Two DDR3 DRAMs on the FPGA Core Board 20 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 21 DDR3_DQ [14] PS_DDR_DQ15_502 DDR3_DQ [15] PS_DDR_DQ16_502 DDR3_DQ [16] PS_DDR_DQ17_502 DDR3_DQ [17] PS_DDR_DQ18_502 DDR3_DQ [18] PS_DDR_DQ19_502 DDR3_DQ [19] PS_DDR_DQ20_502 DDR3_DQ [20] PS_DDR_DQ21_502 DDR3_DQ [21] PS_DDR_DQ22_502 DDR3_DQ [22] PS_DDR_DQ23_502 DDR3_DQ [23] PS_DDR_DQ24_502 DDR3_DQ [24] PS_DDR_DQ25_502 DDR3_DQ [25] 21 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 22 PS_DDR_A9_502 DDR3_A[9] PS_DDR_A10_502 DDR3_A[10] PS_DDR_A11_502 DDR3_A[11] PS_DDR_A12_502 DDR3_A[12] PS_DDR_A13_502 DDR3_A[13] PS_DDR_A14_502 DDR3_A[14] PS_DDR_BA0_502 DDR3_BA[0] PS_DDR_BA1_502 DDR3_BA[1] PS_DDR_BA2_502 DDR3_BA[2] PS_DDR_CS_B_502 DDR3_S0 PS_DDR_RAS_B_502 DDR3_RAS PS_DDR_CAS_B_502 DDR3_CAS PS_DDR_WE_B_502 DDR3_WE PS_DDR_ODT_502 DDR3_ODT PS_DDR_DRST_B_502 DDR3_RESET PS_DDR_CKP_502 DDR3_CLK_P PS_DDR_CKN_502 DDR3_CLK_N 22 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 23: Part 6.3: Gigabit Ethernet Interface

    When the network is connected to 100M Ethernet, the data transmission of ZYNQ and PHY chip KSZ9031RNX is communicated through RMII bus, and the transmission clock is 25Mhz. Data is sampled on the rising edge and falling 23 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 24 ZYNQ Pin Number Description PS_MIO16_501 RGMII Transmit Clock ETH_GCLK PS_MIO17_501 Transmit data bit0 ETH_TXD0 PS_MIO18_501 Transmit data bit1 ETH_TXD1 PS_MIO19_501 Transmit data bit2 ETH_TXD2 PS_MIO20_501 Transmit data bit3 ETH_TXD3 PS_MIO21_501 Transmit enable signal ETH_TXCTL 24 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 25: Part 6.4: Usb2.0 Interface

    USB and other slave peripherals J5 and J6 not OTG Mode FPGA core board as a slave device, USB port to installation jumper connect to the computer caps Table 6-3: The USB interface mode switching instructions 25 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 26 Figure 6-7: The USB3320C chip on the FPGA Board USB2.0 Pin Assignment： Signal Name ZYNQ Pin Name ZYNQ Pin Number Description OTG_DATA4 PS_MIO28_501 USB Data Bit4 OTG_DIR PS_MIO29_501 USB Data Direction Signal OTG_STP PS_MIO30_501 USB Stop Signal 26 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 27: Part 6.5: Usb To Serial Port

    BANK501 of the ZYNQ EPP. Since the VCCMIO of the BANK is set to 1.8V, the data level of the CP2102GM is 3.3V, which is connected by the TXS0102DCUR level conversion chip. Figure 6-8 detailed the schematic diagram of the CP2102GM and ZYNQ connections Figure 6-8: CP2102GM Connection Diagram 27 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 28: Part 6.6: Sd Card Slot

    ZYNQ chip, the Linux operating system kernel, the file system and other user data files. The SDIO signal is connected to the IO signal of the PS BANK501 of ZYNQ. Since the VCCMIO of the BANK is set to 1.8V, but the data level of the 28 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 29 Description Number SD_CLK PS_MIO40 SD Clock Signal SD_CMD PS_MIO41 SD Command Signal SD_D0 PS_MIO42 SD Data0 SD_D1 PS_MIO43 SD Data1 SD_D2 PS_MIO44 SD Data2 SD_D3 PS_MIO45 SD Data3 SD_CD PS_MIO47 SD Card Insertion Signal 29 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 30: Part 6.7: User Leds

    On the AC7010/AC7020 core board, the entire ZYNQ system is reset by a RESET key, and the reset signal is connected to the PS pin's reset pin PS_POR_B_500. The user can use this user key to manually reset. In the 30 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 31: Part 7：Zynq Pl Peripherals

    The PL part of the AC7010/AC7020 FPGA core board is also connected to one LED light-emitting diode. The schematic diagram is shown in Figure 7-1, The LED signal is connected to the IO of the PL part BANK34. When the IO 31 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 32: Part 7.2: Expansion Port J10

    The expansion port J10 is a 40-pin 2.54mm double-row connector, which expands more peripherals and interfaces for users. The default is not soldered, the user can solder to a double-row male connectors or female connectors as 32 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 33 FPGA. If you want to connect 5V equipment, you need to connect level conversion chip. The circuit of the expansion port (J10) is shown in Figure 7-3: Figure 7-3: Expansion header J10 schematic Figure 7-4: Expansion header J10 on the FPGA Board 33 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 34 PIN18 IO34_L6N PIN19 IO34_L5N PIN20 IO34_L5P PIN21 IO34_L3N PIN22 IO34_L3P PIN23 IO34_L4P PIN24 IO34_L4N PIN25 IO34_L2N PIN26 IO34_L2P PIN27 IO34_L1N PIN28 IO34_L1P PIN29 PS_MIO9 PIN30 PS_MIO14 PIN31 PS_MIO11 PIN32 PS_MIO8 PIN33 PS_MIO13 PIN34 PS_MIO15 34 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 35: Part 7.3: Expansion Port J11

    The expansion port J11, which expands more peripherals and interfaces for users. Currently, the J11 interface can be directly connected to the module provided by ALINX, include: ADDA module, LCD module, Gigabit Ethernet module, audio input/output module, matrix keyboard module, 500W binocular vision camera module, etc.
  • Page 36 J11 Expansion Header Pin Assignment J11 Pin Signal Name ZYNQ Pin Number PIN1 PIN2 PIN3 IO34_L23P PIN4 IO34_L23N PIN5 IO34_L24P PIN6 IO34_L24N PIN7 IO35_L9N PIN8 IO35_L9P PIN9 IO35_L7N PIN10 IO35_L7P PIN11 IO34_L20P PIN12 IO34_L20N PIN13 IO34_L15N 36 / 40 Amazon Store: https://www.amazon.com/alinx...

  • Page 37: Part 7.4: Expansion Port J12

    The J12 interface can be directly connected to the module provided by ALINX. The expansion port J12, which expands more peripherals and 37 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 38 ZYNQ FPGA Development Board AC7010/AC7020 User Manual interfaces for users. Currently, the J12 interface can be directly connected to the module provided by ALINX, include: ADDA module, LCD module, Gigabit Ethernet module, audio input/output module, matrix keyboard module, 500W binocular vision camera module, etc.
  • Page 39 PIN18 IO35_L13N PIN19 IO35_L10N PIN20 IO35_L10P PIN21 IO35_L19P PIN22 IO35_L19N PIN23 IO35_L20P PIN24 IO35_L20N PIN25 IO35_L8P PIN26 IO35_L8N PIN27 IO35_L2P PIN28 IO35_L2N PIN29 PS_MIO9 PIN30 PS_MIO14 PIN31 PS_MIO11 PIN32 PS_MIO8 PIN33 PS_MIO13 PIN34 PS_MIO15 39 / 40 Amazon Store: https://www.amazon.com/alinx...
  • Page 40 ZYNQ FPGA Development Board AC7010/AC7020 User Manual PIN35 PS_MIO10 PIN36 PS_MIO12 PIN37 PIN38 PIN39 +3.3V PIN40 +3.3V 40 / 40 Amazon Store: https://www.amazon.com/alinx...

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