Part 2.3: Ddr4 Dram - Alinx ZYNQ UltraScale+ User Manual

 Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,
2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO
 Power management: Support the four-part division of power supply
Full/Low/PL/Battery
 Encryption algorithm: support RSA, AES and SHA.
 System monitoring: 10-bit 1Mbps AD sampling for temperature and
voltage detection.
The main parameters of the PL logic part are as follows:
 Logic Cells: 600K
 CLB Flip-flops: 548K
 Look-up-tables (LUTs): 274K
 Block RAM: 32.1Mb
 Clock Management Units (CMTs): 4
 DSP Slices: 2520
 GTH 16.3Gb/s Transceiver: 24
XCZU9EG-2FFVB1156I chip speed grade is -2, industrial grade, package
is FFVB1156.

Part 2.3: DDR4 DRAM

The ACU9EG core board is equipped with 6 Micron (Micron) 1GB DDR4
chips, model MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on
the PS side to form a 64-bit data bus bandwidth and 4GB capacity. Two DDR4
chip is mounted on the PL end, which is a 32-bit data bus width and a capacity
of 2GB. The maximum operating speed of the DDR4 SDRAM on the PS side
can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems
are directly connected to the memory interface of the PS BANK504. The
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ZYNQ Ultrascale + FPGA Board AXU9EG User Manual
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