Alinx ZYNQ UltraScale+ User Manual page 34

77 PS_MIO43
79 PS_MIO41
81
83 PS_MIO44
85 SD_CD
87 SD_D0
89 SD_D3
91
93 SD_D1
95 SD_D2
97 SD_CLK
99 SD_CMD
101
103 VCCO_66
105 VCCO_66
107
109
111
113
115
117
119
Pin assignment of board to board connector J31
J31 connects the IO of BANK40, BANK50, BANK66, and BANK67.
BANK25, BANK26, IO of BANK66 and the GTX signal of BANK505;
standard of BANK66, 67 is determined by the VCCO_66 and VCCO_67 power
supply of the carrier board, the carrier board provides +1.8V by default.
J31 Pin Signal Name
3
5
7
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ZYNQ Ultrascale + FPGA Board AXU9EG User Manual
K24
J24
GND
N24
P24
J25
K25
GND
L25
M25
N25
P25
GND
GND
+12V
+12V
+12V
+12V
+12V
+12V
Pin
Number
POWER_SW
PS_MODE3
PS_MODE2
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78
80
- 82
84
86
88
90
- 92
94
96
98
100
- 102
- 104
- 106
- 108
- 110
- 112
- 114
- 116
- 118
- 120
J31 Pin
2
- 4
R23 6
T23 8
PHY1_TXD2
PHY1_TXD3
GND
PHY1_TXCK
PHY1_TXCTL
PHY1_RXD3
PHY1_RXD2
GND
PHY1_RXD1
PHY1_RXD0
PHY1_RXCTL
PHY1_RXCK
GND
VCCO_67
VCCO_67
GND
+12V
+12V
+12V
+12V
+12V
+12V
Signal Name Pin
Number
FPGA_TCK
FPGA_TMS
FPGA_TDO
FPGA_TDI
B25
B26
-
A25
B27
G25
H24
-
E25
C27
D25
C26
-
-
-
-
-
-
-
-
-
-
the level
R25
R24
T25
U25