Xilinx AC701 User Manual page 37

Table 1-15: Ethernet PHY U12 Configuration Pin Settings
The Ethernet connections from the XC7A200T at U1 to the 88E1116R PHY device at U12 are
listed in
Table 1-16: Ethernet PHY U12 Connections to FPGA U1
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
U12 Pin Name (No.)
CONFIG0 (64)
CONFIG1 (1)
CONFIG2 (2)
CONFIG3 (3)
Table 1-16 Ethernet PHY Connections to FPGA U1.
FPGA U1 Pin Number
T14
W18
U22
T15
T17
T18
U15
U16
U21
U14
V14
V16
V17
U17
V18
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Setting
VCCO1V8 PHYAD[1]=1
PHY_LED0 PHYAD[3]=0
GND ENA_XC=0
PHY_LED0 ENA_XC=0
VCC1V8 ENA_XC=1
GND RGMII_TX=0
PHY_LED0 RGMII_TX=0
PHY_LED1 RGMII_TX=1
VCC1V8 RGMII_TX=1
Schematic Net Name
PHY_MDIO
PHY_MDC
PHY_TX_CLK
PHY_TX_CTRL
PHY_TXD3
PHY_TXD2
PHY_TXD1
PHY_TXD0
PHY_RX_CLK
PHY_RX_CTRL
PHY_RXD3
PHY_RXD2
PHY_RXD1
PHY_RXD0
PHY_RESET_B
Feature Descriptions
Configuration
PHYAD[0]=1
PHYAD[2]=1
PHYAD[4]=0
PHYAD[4]=1
PHYAD[4]=1
RGMII_RX=0
RGMII_RX=1
RGMII_RX=0
RGMII_RX=1
M88E1116R U12
Pin Name
45 MDIO
48 MDC
60 TX_CLK
63 TX_CTRL
62 TXD3
61 TXD2
59 TXD1
58 TXD0
53 RX_CLK
49 RX_CTRL
55 RXD3
54 RXD2
51 RXD1
50 RXD0
10 RESET_B
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