Xilinx AC701 User Manual page 50

Chapter 1: AC701 Evaluation Board Features
GPIO DIP Switch
[Figure
Figure 1-30
X-Ref Target - Figure 1-30
Figure 1-28 shows the LCD J23 2x7 male pin header.
X-Ref Target - Figure 1-31
Figure 1-29 shows the J48 PMOD male pin header.
X-Ref Target - Figure 1-32
50
1-2, callout 23]
shows the GPIO DIP Switch circuit.
GPIO_DIP_SW0
GPIO_DIP_SW1
GPIO_DIP_SW2
GPIO_DIP_SW3
R53
4.7kΩ
0.1 W
5%
GND
Figure 1-30: GPIO DIP Switch
J23
LCD_DB7 1 2
LCD_DB5 3 4
NC 5 6
NC 7 8
LCD_E 9 10
LCD_RS 11 12
13 14
GND
Figure 1-31: LCD Header J23
Figure 1-32: PMOD Header J48
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1
2
3
4
SDA04H1SBD
R52 R50
4.7kΩ 4.7kΩ
0.1 W 0.1 W
5% 5%
R51
4.7kΩ
0.1 W
5%
VCC5V0
VCC5V0
LCD_DB6
LCD_DB4
R118
NC
6.81kΩ
NC
LCD_RW
LCD_VEE
GND
VCC3V3
J48
PMOD_0 1
PMOD_1 2
PMOD_2 3
PMOD_3 4
5
6
HDR_1X6
GND
UG952_c1_32_100412
SW2 FPGA_1V5
8
7
6
5
UG952_c1_30_100412
R232
LCD Contrast
2 kΩ
Potentiometer
UG952_c1_31_100412
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012