Xilinx AC701 User Manual page 27

Jitter Attenuated Clock
[Figure
The AC701 board includes a Silicon Labs Si5324 jitter attenuator U24 on the back side of the
board. FPGA user logic can implement a clock recovery circuit and then output this clock
to a differential I/O pair on I/O bank 16 (REC_CLOCK_C_P, FPGA U1 pin D23 and
REC_CLOCK_C_N, FPGA U1 pin D24) for jitter attenuation. Duplicate capacitively
coupled jitter attenuated clocks are routed to a pair of MGT clock MUXes U3 and U4. See
Table 1-9, page
The primary purpose of this clock is to support CPRI/OBSAI applications that perform
clock recovery from a user-supplied SFP/SFP+ module and use the jitter attenuated
recovered clock to drive the reference clock inputs of a GTP transceiver. The jitter
attenuated clock circuit is shown in
X-Ref Target - Figure 1-15
X6
114.285 MHz
20 ppm
XA
2
GND1
GND2 XB
4
GND
REC_CLOCK_C_P
R167
100Ω
REC_CLOCK_C_N
SI5324_INT_ALM_B
SI5324_VCC
SI5326_RST_B
See the Silicon Labs Si5324 datasheet for more information on this device
www.silabs.com. The SI5324 U24 connections to FPGA U1 are shown in
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
1-2, callout 10]
25.
SI5324_VCC
5
10
32
1
SI5324_XTAL_XA 6
3
SI5324_XTAL_XB 7
C33
0.1μF 25V
X5R
REC_CLOCK_P 16
REC_CLOCK_N 17
NC 12
C34
0.1μF 25V
NC 13
X5R
3
NC 4
R4
NC 11
4.7K
NC 15
NC 18
NC 19
R292
NC 20
4.7K
1
21
R424
4.7KΩ 5%
GND
Figure 1-15: Jitter Attenuated Clock
www.xilinx.com
Figure 1-15.
U24
Si5324C-C-GM
Clock Multiplier/
Jitter Attenuator
2
NC
VDDA NC1
2
NC
VDDA NC2
2
NC
VDDA NC3
5
NC
XA NC4
8
NC
NC5
29
SI5324_OUT_N
XB CKOUT1_N
28
SI5324_OUT_P
CKOUT1_P
35
CKIN1_P SI5324_OUT_P
CKOUT2_N
34
SI5324_OUT_N
CKOUT2_P
CKIN1_N
CKIN2_P
CKIN2_N
37
GNDPAD
36
INT_C1B CMODE
27
C2B SDI
23
RATE0 SDA_SDO
22
RATE1 SCL
24
LOL A0
31
DEC A1
31
INC A2_SS
9
RST_B GND1
31
CS_CA GND2
GND
Feature Descriptions
C31
0.1μF 25V
X5R
SI5324_OUT_C_N
SI5324_OUT_C_P
C32
0.1μF 25V
X5R
C9
0.1μF 25V
X5R
SI5324_OUT_C_P
SI5324_OUT_C_N
C10
0.1μF 25V
X5R
NC
SI5324_SDA
SI5324_SCL
UG952_c1_15_100212
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Table 1-9.
27