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Chapter 1: AC701 Evaluation Board Features
X-Ref Target - Figure 1-17
SMA_MGT_REFCLK_P
SMA_MGT_REFCLK_N
SI5324_OUT1_C_P
SI5324_OUT1_C_N
FMC1_HBC_GBTCLK1_M2C_C_P
FMC1_HBC_GBTCLK1_M2C_C_N
PCIE_MGT_CLK_SEL0
PCIE_MGT_CLK_SEL1
30
VCC2V5
SY89544UMG
1
VCC1
5
VCC2
4
IN0
50
3
VT0
NC
50
2
IN0
32
IN1
50
31
NC
VT1
50
30
IN1
27
IN2
50
26
NC
VT2
50
25
IN2
23
NC
IN3
50
22
NC
VT3
50
21
NC
IN3
6
SEL0
19
SEL1
MGT_CLK1_SEL1
MGT_CLK1_SEL0
R151
10K
1/10W
1%
R152
10K
1/10W
1%
Figure 1-17: MGT Clock MUX U4 Circuit
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U4
VCC3
VCC4
VCC5
0
VCC6
VCC7
VCC8
1
Q
Q
GND1
2
GND2
GND3
GND4
3
S1
GND5
S0
GND6
PWRPAD
VCC2V5
R452
10K
1/10W
1%
Q23
NDS336P
460 mW
GND
VCC2V5
R453
10K
1/10W
1%
Q22
NDS336P
460 mW
GND
VCC2V5
C106
8
0.1μF
25V
17
X5R
20
GND
24
C321
28
0.1μF
25V
29
X5R
SFP_MGT_CLK1_P
10
SFP_MGT_CLK1_P
11
7
C322
TO MGT BANK 213
0.1μF
MGTREFCLK1_P/N
9
25V
PINS AA11, AB11
X5R
12
13
16
18
33
GND
UG952_c1_17_101612
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
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