Xilinx AC701 User Manual page 23

Programmable User Clock Source
[Figure
The AC701 board has a programmable low-jitter 3.3V differential oscillator (U34) driving
the FPGA MRCC inputs of bank 14. This USER_CLOCK_P and USER_CLOCK_N clock
signal pair are connected to FPGA U1 pins M21 and M22 respectively. On power-up the
user clock defaults to an output frequency of 156.250 MHz. User applications can change
the output frequency within the range of 10 MHz to 810 MHz through an I
Power cycling the AC701 board will revert the user clock to its default frequency of
156.250 MHz.
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The user clock circuit is shown in
X-Ref Target - Figure 1-11
References
The Silicon Labs Si570 data sheet is available from http://www.silabs.com.
Reference design files are available to demonstrate how to program the Si570
programmable oscillator. See:
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•
•
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AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
1-2, callout 7]
Programmable Oscillator: Silicon Labs Si570BAB000544DG (10 MHz - 810 MHz)
Differential Output
VCC3V3
R15
4.7KΩ 5%
USER CLOCK SDA
To I 2 C
Bus Switch
USER CLOCK SCL
(U49)
GND
Figure 1-11: User Clock Source
XTP230, AC701 Si570 Programming
RDF0228, Reference Design Files
XTP229, AC701 Si570 Fixed Frequencies
RDF0227, Reference Design Files
www.xilinx.com
Figure 1-11.
U34
Si570
Programmable
Oscillator
1 6
NC VDD
2
OE
7
USER CLOCK N
SDA 5
CLK-
8
4 USER CLOCK P
SCL CLK+
3
GND
Feature Descriptions
2
C interface.
VCC3V3
C192
0.01 μF 25V
X7R
GND
10 MHz - 810 MHz
UG952_c1_11_101512
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