Xadc Header - Xilinx AC701 User Manual

X-Ref Target - Figure 1-38

XADC Header

[Figure
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
J61
3
Fan Tach
2
Cooling
Fan +12V
Fan
1
Fan GND
VCC2V5
SM_FAN_PWM
FPGA
U1 Pin J26
Figure 1-38: FPGA Cooling Fan Circuit
1-2, callout 31]
7 series FPGAs provide an Analog Front End (XADC) block. The XADC block includes
a dual 12-bit, 1 MSPS Analog-to-Digital Convertor (ADC) and on-chip sensors. See
UG480, 7 Series FPGAs XADC Dual 12-Bit 1MSPS Analog-to-Digital Converter User Guide
for details on the capabilities of the analog front end.
board XADC support features.
www.xilinx.com
VCC12_P
R245 R393
10.0K 1% 10.0K 1%
1/10W 1/10W
R390
D14 4.75K 1%
100V 1/10W
500 mW
DL4148
2 4
R277
Q17
1.00K 1%
NDT30555L
1/16W
1
1.3 W
3
GND
Feature Descriptions
SM_FAN_TACH
U1 Pin J25
D15
2.7V
500 mW
MM3Z2V7B
GND
UG952_c1_38_100512
Figure 1-39 shows the AC701
FPGA
65