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Appendix C: Master UCF Listing
NET
FMC1_HPC_HA19_P
NET
FMC1_HPC_HA19_N
NET
FMC1_HPC_HA20_P
NET
FMC1_HPC_HA20_N
NET
FMC1_HPC_HA21_P
NET
FMC1_HPC_HA21_N
NET
FMC1_HPC_HA22_P
NET
FMC1_HPC_HA22_N
NET
FMC1_HPC_HA23_P
NET
FMC1_HPC_HA23_N
#NET
No Connect
NET
HDMI_R_D21
NET
HDMI_R_D16
NET
HDMI_R_D11
NET
HDMI_R_D7
NET
HDMI_R_D8
NET
HDMI_R_DE
NET
HDMI_R_VSYNC
NET
HDMI_R_D9
NET
HDMI_R_D6
NET
HDMI_R_D5
NET
HDMI_R_D29
NET
HDMI_R_D17
NET
HDMI_R_D10
NET
HDMI_R_D4
NET
HDMI_R_D30
NET
HDMI_R_HSYNC
NET
HDMI_R_D28
NET
HDMI_R_D32
NET
HDMI_R_D31
NET
HDMI_R_D23
NET
HDMI_R_D19
NET
HDMI_R_D33
NET
HDMI_R_D34
NET
PHY_TX_CLK
NET
HDMI_R_D35
NET
PHY_RX_CLK
NET
HDMI_R_CLK
NET
HDMI_INT
NET
HDMI_R_SPDIF
NET
HDMI_SPDIF_OUT_LS
NET
HDMI_R_D18
NET
HDMI_R_D20
NET
HDMI_R_D22
NET
USB_UART_TX
NET
USB_UART_RX
NET
USB_UART_RTS
NET
USB_UART_CTS
NET
PHY_RESET_B
NET
PHY_MDC
NET
PHY_MDIO
NET
PHY_TX_CTRL
NET
PHY_TXD3
NET
PHY_TXD2
NET
PHY_TXD1
NET
PHY_TXD0
NET
PHY_RX_CTRL
NET
PHY_RXD3
NET
PHY_RXD2
NET
PHY_RXD1
NET
PHY_RXD0
NET
SI5324_INT_ALM_B
NET
FLASH_D0
NET
FLASH_D1
NET
FLASH_D2
NET
FLASH_D3
NET
CTRL2_PWRGOOD
NET
FPGA_EMCCLK
NET
FMC1_HPC_PRSNT_M2C_B
NET
FMC1_HPC_PG_M2C
NET
FMC_VADJ_ON_B
NET
IIC_MUX_RESET_B
NET
QSPI_IC_CS_B
NET
IIC_SCL_MAIN
NET
IIC_SDA_MAIN
NET
PCIE_WAKE_B
NET
PCIE_PERST
NET
LCD_E_LS
NET
LCD_RW_LS
NET
LCD_DB4_LS
NET
LCD_DB5_LS
78
LOC = AC17 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD17 | IOSTANDARD=LVCMOS25; # Bank
LOC = Y16
| IOSTANDARD=LVCMOS25; # Bank
LOC = Y17
| IOSTANDARD=LVCMOS25; # Bank
LOC = AB16 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC16 | IOSTANDARD=LVCMOS25; # Bank
LOC = Y15
| IOSTANDARD=LVCMOS25; # Bank
LOC = AA15 | IOSTANDARD=LVCMOS25; # Bank
LOC = W14
| IOSTANDARD=LVCMOS25; # Bank
LOC = W15
| IOSTANDARD=LVCMOS25; # Bank
LOC = W16
| IOSTANDARD=LVCMOS25; # Bank
LOC = U24
| IOSTANDARD=LVCMOS25; # Bank
LOC = U25
| IOSTANDARD=LVCMOS25; # Bank
LOC = U26
| IOSTANDARD=LVCMOS25; # Bank
LOC = V26
| IOSTANDARD=LVCMOS25; # Bank
LOC = W26
| IOSTANDARD=LVCMOS25; # Bank
LOC = AB26 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC26 | IOSTANDARD=LVCMOS25; # Bank
LOC = W25
| IOSTANDARD=LVCMOS25; # Bank
LOC = Y26
| IOSTANDARD=LVCMOS25; # Bank
LOC = Y25
| IOSTANDARD=LVCMOS25; # Bank
LOC = AA25 | IOSTANDARD=LVCMOS25; # Bank
LOC = V24
| IOSTANDARD=LVCMOS25; # Bank
LOC = W24
| IOSTANDARD=LVCMOS25; # Bank
LOC = AA24 | IOSTANDARD=LVCMOS25; # Bank
LOC = AB25 | IOSTANDARD=LVCMOS25; # Bank
LOC = AA22 | IOSTANDARD=LVCMOS25; # Bank
LOC = AA23 | IOSTANDARD=LVCMOS25; # Bank
LOC = AB24 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC24 | IOSTANDARD=LVCMOS25; # Bank
LOC = V23
| IOSTANDARD=LVCMOS25; # Bank
LOC = W23
| IOSTANDARD=LVCMOS25; # Bank
LOC = Y22
| IOSTANDARD=LVCMOS25; # Bank
LOC = Y23
| IOSTANDARD=LVCMOS25; # Bank
LOC = U22
| IOSTANDARD=LVCMOS25; # Bank
LOC = V22
| IOSTANDARD=LVCMOS25; # Bank
LOC = U21
| IOSTANDARD=LVCMOS25; # Bank
LOC = V21
| IOSTANDARD=LVCMOS25; # Bank
LOC = W21
| IOSTANDARD=LVCMOS25; # Bank
LOC = Y21
| IOSTANDARD=LVCMOS25; # Bank
LOC = T20
| IOSTANDARD=LVCMOS25; # Bank
LOC = U20
| IOSTANDARD=LVCMOS25; # Bank
LOC = W20
| IOSTANDARD=LVCMOS25; # Bank
LOC = Y20
| IOSTANDARD=LVCMOS25; # Bank
LOC = T19
| IOSTANDARD=LVCMOS25; # Bank
LOC = U19
| IOSTANDARD=LVCMOS25; # Bank
LOC = V19
| IOSTANDARD=LVCMOS25; # Bank
LOC = W19
| IOSTANDARD=LVCMOS25; # Bank
LOC = V18
| IOSTANDARD=LVCMOS25; # Bank
LOC = W18
| IOSTANDARD=LVCMOS25; # Bank
LOC = T14
| IOSTANDARD=LVCMOS25; # Bank
LOC = T15
| IOSTANDARD=LVCMOS25; # Bank
LOC = T17
| IOSTANDARD=LVCMOS25; # Bank
LOC = T18
| IOSTANDARD=LVCMOS25; # Bank
LOC = U15
| IOSTANDARD=LVCMOS25; # Bank
LOC = U16
| IOSTANDARD=LVCMOS25; # Bank
LOC = U14
| IOSTANDARD=LVCMOS25; # Bank
LOC = V14
| IOSTANDARD=LVCMOS25; # Bank
LOC = V16
| IOSTANDARD=LVCMOS25; # Bank
LOC = V17
| IOSTANDARD=LVCMOS25; # Bank
LOC = U17
| IOSTANDARD=LVCMOS25; # Bank
LOC = M19
| IOSTANDARD=LVCMOS33; # Bank
LOC = R14
| IOSTANDARD=LVCMOS33; # Bank
LOC = R15
| IOSTANDARD=LVCMOS33; # Bank
LOC = P14
| IOSTANDARD=LVCMOS33; # Bank
LOC = N14
| IOSTANDARD=LVCMOS33; # Bank
LOC = P15
| IOSTANDARD=LVCMOS33; # Bank
LOC = P16
| IOSTANDARD=LVCMOS33; # Bank
LOC = N16
| IOSTANDARD=LVCMOS33; # Bank
LOC = N17
| IOSTANDARD=LVCMOS33; # Bank
LOC = R16
| IOSTANDARD=LVCMOS33; # Bank
LOC = R17
| IOSTANDARD=LVCMOS33; # Bank
LOC = P18
| IOSTANDARD=LVCMOS33; # Bank
LOC = N18
| IOSTANDARD=LVCMOS33; # Bank
LOC = K25
| IOSTANDARD=LVCMOS33; # Bank
LOC = K26
| IOSTANDARD=LVCMOS33; # Bank
LOC = M20
| IOSTANDARD=LVCMOS33; # Bank
LOC = L20
| IOSTANDARD=LVCMOS33; # Bank
LOC = L24
| IOSTANDARD=LVCMOS33; # Bank
LOC = L25
| IOSTANDARD=LVCMOS33; # Bank
LOC = M24
| IOSTANDARD=LVCMOS33; # Bank
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12 VCCO - VCCO_VADJ - IO_L20P_T3_12
12 VCCO - VCCO_VADJ - IO_L20N_T3_12
12 VCCO - VCCO_VADJ - IO_L21P_T3_DQS_12
12 VCCO - VCCO_VADJ - IO_L21N_T3_DQS_12
12 VCCO - VCCO_VADJ - IO_L22P_T3_12
12 VCCO - VCCO_VADJ - IO_L22N_T3_12
12 VCCO - VCCO_VADJ - IO_L23P_T3_12
12 VCCO - VCCO_VADJ - IO_L23N_T3_12
12 VCCO - VCCO_VADJ - IO_L24P_T3_12
12 VCCO - VCCO_VADJ - IO_L24N_T3_12
12 VCCO - VCCO_VADJ - IO_25_12
13 VCCO - FPGA_1V8 - IO_0_13
13 VCCO - FPGA_1V8 - IO_L1P_T0_13
13 VCCO - FPGA_1V8 - IO_L1N_T0_13
13 VCCO - FPGA_1V8 - IO_L2P_T0_13
13 VCCO - FPGA_1V8 - IO_L2N_T0_13
13 VCCO - FPGA_1V8 - IO_L3P_T0_DQS_13
13 VCCO - FPGA_1V8 - IO_L3N_T0_DQS_13
13 VCCO - FPGA_1V8 - IO_L4P_T0_13
13 VCCO - FPGA_1V8 - IO_L4N_T0_13
13 VCCO - FPGA_1V8 - IO_L5P_T0_13
13 VCCO - FPGA_1V8 - IO_L5N_T0_13
13 VCCO - FPGA_1V8 - IO_L6P_T0_13
13 VCCO - FPGA_1V8 - IO_L6N_T0_VREF_13
13 VCCO - FPGA_1V8 - IO_L7P_T1_13
13 VCCO - FPGA_1V8 - IO_L7N_T1_13
13 VCCO - FPGA_1V8 - IO_L8P_T1_13
13 VCCO - FPGA_1V8 - IO_L8N_T1_13
13 VCCO - FPGA_1V8 - IO_L9P_T1_DQS_13
13 VCCO - FPGA_1V8 - IO_L9N_T1_DQS_13
13 VCCO - FPGA_1V8 - IO_L10P_T1_13
13 VCCO - FPGA_1V8 - IO_L10N_T1_13
13 VCCO - FPGA_1V8 - IO_L11P_T1_SRCC_13
13 VCCO - FPGA_1V8 - IO_L11N_T1_SRCC_13
13 VCCO - FPGA_1V8 - IO_L12P_T1_MRCC_13
13 VCCO - FPGA_1V8 - IO_L12N_T1_MRCC_13
13 VCCO - FPGA_1V8 - IO_L13P_T2_MRCC_13
13 VCCO - FPGA_1V8 - IO_L13N_T2_MRCC_13
13 VCCO - FPGA_1V8 - IO_L14P_T2_SRCC_13
13 VCCO - FPGA_1V8 - IO_L14N_T2_SRCC_13
13 VCCO - FPGA_1V8 - IO_L15P_T2_DQS_13
13 VCCO - FPGA_1V8 - IO_L15N_T2_DQS_13
13 VCCO - FPGA_1V8 - IO_L16P_T2_13
13 VCCO - FPGA_1V8 - IO_L16N_T2_13
13 VCCO - FPGA_1V8 - IO_L17P_T2_13
13 VCCO - FPGA_1V8 - IO_L17N_T2_13
13 VCCO - FPGA_1V8 - IO_L18P_T2_13
13 VCCO - FPGA_1V8 - IO_L18N_T2_13
13 VCCO - FPGA_1V8 - IO_L19P_T3_13
13 VCCO - FPGA_1V8 - IO_L19N_T3_VREF_13
13 VCCO - FPGA_1V8 - IO_L20P_T3_13
13 VCCO - FPGA_1V8 - IO_L20N_T3_13
13 VCCO - FPGA_1V8 - IO_L21P_T3_DQS_13
13 VCCO - FPGA_1V8 - IO_L21N_T3_DQS_13
13 VCCO - FPGA_1V8 - IO_L22P_T3_13
13 VCCO - FPGA_1V8 - IO_L22N_T3_13
13 VCCO - FPGA_1V8 - IO_L23P_T3_13
13 VCCO - FPGA_1V8 - IO_L23N_T3_13
13 VCCO - FPGA_1V8 - IO_L24P_T3_13
13 VCCO - FPGA_1V8 - IO_L24N_T3_13
13 VCCO - FPGA_1V8 - IO_25_13
14 VCCO - FPGA_3V3 - IO_0_14
14 VCCO - FPGA_3V3 - IO_L1P_T0_D00_MOSI_14
14 VCCO - FPGA_3V3 - IO_L1N_T0_D01_DIN_14
14 VCCO - FPGA_3V3 - IO_L2P_T0_D02_14
14 VCCO - FPGA_3V3 - IO_L2N_T0_D03_14
14 VCCO - FPGA_3V3 - IO_L3P_T0_DQS_PUDC_B_14
14 VCCO - FPGA_3V3 - IO_L3N_T0_DQS_EMCCLK_14
14 VCCO - FPGA_3V3 - IO_L4P_T0_D04_14
14 VCCO - FPGA_3V3 - IO_L4N_T0_D05_14
14 VCCO - FPGA_3V3 - IO_L5P_T0_D06_14
14 VCCO - FPGA_3V3 - IO_L5N_T0_D07_14
14 VCCO - FPGA_3V3 - IO_L6P_T0_FCS_B_14
14 VCCO - FPGA_3V3 - IO_L6N_T0_D08_VREF_14
14 VCCO - FPGA_3V3 - IO_L7P_T1_D09_14
14 VCCO - FPGA_3V3 - IO_L7N_T1_D10_14
14 VCCO - FPGA_3V3 - IO_L8P_T1_D11_14
14 VCCO - FPGA_3V3 - IO_L8N_T1_D12_14
14 VCCO - FPGA_3V3 - IO_L9P_T1_DQS_14
14 VCCO - FPGA_3V3 - IO_L9N_T1_DQS_D13_14
14 VCCO - FPGA_3V3 - IO_L10P_T1_D14_14
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
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