Xilinx AC701 User Manual page 79

NET LCD_DB6_LS
NET LCD_DB7_LS
NET LCD_RS_LS
NET USER_CLOCK_P
NET USER_CLOCK_N
NET ROTARY_PUSH
NET ROTARY_INCA
NET ROTARY_INCB
NET SDIO_CD_DAT3
NET SDIO_CMD
NET SDIO_CLK
NET SDIO_DAT0
NET SDIO_DAT1
NET SDIO_DAT2
NET SDIO_SDDET
NET SDIO_SDWP
NET PMBUS_CLK_LS
NET PMBUS_DATA_LS
NET PMBUS_CTRL_LS
NET PMBUS_ALERT_LS
NET GPIO_LED_0
NET GPIO_LED_1
NET GPIO_LED_2
NET GPIO_LED_3
NET PMOD_0
NET PMOD_1
NET PMOD_2
NET PMOD_3
NET SFP_LOS
NET SFP_TX_DISABLE
NET XADC_GPIO_2
NET XADC_VAUX0_R_P
NET XADC_VAUX0_R_N
NET XADC_VAUX8_R_P
NET XADC_VAUX8_R_N
NET XADC_AD1_R_P
NET XADC_AD1_R_N
NET FMC1_HPC_LA19_P
NET FMC1_HPC_LA19_N
NET XADC_AD9_R_P
NET XADC_AD9_R_N
NET FMC1_HPC_LA20_P
NET FMC1_HPC_LA20_N
NET FMC1_HPC_LA21_P
NET FMC1_HPC_LA21_N
NET FMC1_HPC_LA22_P
NET FMC1_HPC_LA22_N
NET FMC1_HPC_LA23_P
NET FMC1_HPC_LA23_N
NET FMC1_HPC_LA24_P
NET FMC1_HPC_LA24_N
NET FMC1_HPC_LA18_CC_P
NET FMC1_HPC_LA18_CC_N
NET FMC1_HPC_LA17_CC_P
NET FMC1_HPC_LA17_CC_N
NET FMC1_HPC_CLK1_M2C_P
NET FMC1_HPC_CLK1_M2C_N
NET USER_SMA_CLOCK_P
NET USER_SMA_CLOCK_N
NET FMC1_HPC_LA25_P
NET FMC1_HPC_LA25_N
NET FMC1_HPC_LA26_P
NET FMC1_HPC_LA26_N
NET FMC1_HPC_LA27_P
NET FMC1_HPC_LA27_N
NET FMC1_HPC_LA28_P
NET FMC1_HPC_LA28_N
NET FMC1_HPC_LA29_P
NET FMC1_HPC_LA29_N
NET FMC1_HPC_LA30_P
NET FMC1_HPC_LA30_N
NET FMC1_HPC_LA31_P
NET FMC1_HPC_LA31_N
NET FMC1_HPC_LA32_P
NET FMC1_HPC_LA32_N
NET FMC1_HPC_LA33_P
NET FMC1_HPC_LA33_N
NET SM_FAN_TACH
NET SM_FAN_PWM
NET XADC_GPIO_3
NET XADC_GPIO_0
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
LOC = M25 | IOSTANDARD=LVCMOS33; # Bank
LOC = L22 | IOSTANDARD=LVCMOS33; # Bank
LOC = L23 | IOSTANDARD=LVCMOS33; # Bank
LOC = M21 | IOSTANDARD=LVCMOS33; # Bank
LOC = M22 | IOSTANDARD=LVCMOS33; # Bank
LOC = N21 | IOSTANDARD=LVCMOS33; # Bank
LOC = N22 | IOSTANDARD=LVCMOS33; # Bank
LOC = P20 | IOSTANDARD=LVCMOS33; # Bank
LOC = P21 | IOSTANDARD=LVCMOS33; # Bank
LOC = N23 | IOSTANDARD=LVCMOS33; # Bank
LOC = N24 | IOSTANDARD=LVCMOS33; # Bank
LOC = P19 | IOSTANDARD=LVCMOS33; # Bank
LOC = N19 | IOSTANDARD=LVCMOS33; # Bank
LOC = P23 | IOSTANDARD=LVCMOS33; # Bank
LOC = P24 | IOSTANDARD=LVCMOS33; # Bank
LOC = R20 | IOSTANDARD=LVCMOS33; # Bank
LOC = R21 | IOSTANDARD=LVCMOS33; # Bank
LOC = R25 | IOSTANDARD=LVCMOS33; # Bank
LOC = P25 | IOSTANDARD=LVCMOS33; # Bank
LOC = N26 | IOSTANDARD=LVCMOS33; # Bank
LOC = M26 | IOSTANDARD=LVCMOS33; # Bank
LOC = T24 | IOSTANDARD=LVCMOS33; # Bank
LOC = T25 | IOSTANDARD=LVCMOS33; # Bank
LOC = R26 | IOSTANDARD=LVCMOS33; # Bank
LOC = P26 | IOSTANDARD=LVCMOS33; # Bank
LOC = T22 | IOSTANDARD=LVCMOS33; # Bank
LOC = R22 | IOSTANDARD=LVCMOS33; # Bank
LOC = T23 | IOSTANDARD=LVCMOS33; # Bank
LOC = R23 | IOSTANDARD=LVCMOS33; # Bank
LOC = R18 | IOSTANDARD=LVCMOS33; # Bank
LOC = K18 | IOSTANDARD=LVCMOS25; # Bank
LOC = K15 | IOSTANDARD=LVCMOS25; # Bank
LOC = J16 | IOSTANDARD=LVCMOS25; # Bank
LOC = J14 | IOSTANDARD=LVCMOS25; # Bank
LOC = J15 | IOSTANDARD=LVCMOS25; # Bank
LOC = K16 | IOSTANDARD=LVCMOS25; # Bank
LOC = K17 | IOSTANDARD=LVCMOS25; # Bank
LOC = M14 | IOSTANDARD=LVCMOS25; # Bank
LOC = L14 | IOSTANDARD=LVCMOS25; # Bank
LOC = M15 | IOSTANDARD=LVCMOS25; # Bank
LOC = L15 | IOSTANDARD=LVCMOS25; # Bank
LOC = M16 | IOSTANDARD=LVCMOS25; # Bank
LOC = M17 | IOSTANDARD=LVCMOS25; # Bank
LOC = J19 | IOSTANDARD=LVCMOS25; # Bank
LOC = H19 | IOSTANDARD=LVCMOS25; # Bank
LOC = L17 | IOSTANDARD=LVCMOS25; # Bank
LOC = L18 | IOSTANDARD=LVCMOS25; # Bank
LOC = K20 | IOSTANDARD=LVCMOS25; # Bank
LOC = J20 | IOSTANDARD=LVCMOS25; # Bank
LOC = J18 | IOSTANDARD=LVCMOS25; # Bank
LOC = H18 | IOSTANDARD=LVCMOS25; # Bank
LOC = G20 | IOSTANDARD=LVCMOS25; # Bank
LOC = G21 | IOSTANDARD=LVCMOS25; # Bank
LOC = K21 | IOSTANDARD=LVCMOS25; # Bank
LOC = J21 | IOSTANDARD=LVCMOS25; # Bank
LOC = H21 | IOSTANDARD=LVCMOS25; # Bank
LOC = H22 | IOSTANDARD=LVCMOS25; # Bank
LOC = J23 | IOSTANDARD=LVCMOS25; # Bank
LOC = H23 | IOSTANDARD=LVCMOS25; # Bank
LOC = G22 | IOSTANDARD=LVCMOS25; # Bank
LOC = F22 | IOSTANDARD=LVCMOS25; # Bank
LOC = J24 | IOSTANDARD=LVCMOS25; # Bank
LOC = H24 | IOSTANDARD=LVCMOS25; # Bank
LOC = F23 | IOSTANDARD=LVCMOS25; # Bank
LOC = E23 | IOSTANDARD=LVCMOS25; # Bank
LOC = K22 | IOSTANDARD=LVCMOS25; # Bank
LOC = K23 | IOSTANDARD=LVCMOS25; # Bank
LOC = G24 | IOSTANDARD=LVCMOS25; # Bank
LOC = F24 | IOSTANDARD=LVCMOS25; # Bank
LOC = E25 | IOSTANDARD=LVCMOS25; # Bank
LOC = D25 | IOSTANDARD=LVCMOS25; # Bank
LOC = E26 | IOSTANDARD=LVCMOS25; # Bank
LOC = D26 | IOSTANDARD=LVCMOS25; # Bank
LOC = H26 | IOSTANDARD=LVCMOS25; # Bank
LOC = G26 | IOSTANDARD=LVCMOS25; # Bank
LOC = G25 | IOSTANDARD=LVCMOS25; # Bank
LOC = F25 | IOSTANDARD=LVCMOS25; # Bank
LOC = J25 | IOSTANDARD=LVCMOS25; # Bank
LOC = J26 | IOSTANDARD=LVCMOS25; # Bank
LOC = L19 | IOSTANDARD=LVCMOS25; # Bank
LOC = H17 | IOSTANDARD=LVCMOS25; # Bank
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AC701 Board UCF Listing
14 VCCO - FPGA_3V3 - IO_L10N_T1_D15_14
14 VCCO - FPGA_3V3 - IO_L11P_T1_SRCC_14
14 VCCO - FPGA_3V3 - IO_L11N_T1_SRCC_14
14 VCCO - FPGA_3V3 - IO_L12P_T1_MRCC_14
14 VCCO - FPGA_3V3 - IO_L12N_T1_MRCC_14
14 VCCO - FPGA_3V3 - IO_L13P_T2_MRCC_14
14 VCCO - FPGA_3V3 - IO_L13N_T2_MRCC_14
14 VCCO - FPGA_3V3 - IO_L14P_T2_SRCC_14
14 VCCO - FPGA_3V3 - IO_L14N_T2_SRCC_14
14 VCCO - FPGA_3V3 - IO_L15P_T2_DQS_RDWR_B_14
14 VCCO - FPGA_3V3 - IO_L15N_T2_DQS_DOUT_CSO_B_14
14 VCCO - FPGA_3V3 - IO_L16P_T2_CSI_B_14
14 VCCO - FPGA_3V3 - IO_L16N_T2_A15_D31_14
14 VCCO - FPGA_3V3 - IO_L17P_T2_A14_D30_14
14 VCCO - FPGA_3V3 - IO_L17N_T2_A13_D29_14
14 VCCO - FPGA_3V3 - IO_L18P_T2_A12_D28_14
14 VCCO - FPGA_3V3 - IO_L18N_T2_A11_D27_14
14 VCCO - FPGA_3V3 - IO_L19P_T3_A10_D26_14
14 VCCO - FPGA_3V3 - IO_L19N_T3_A09_D25_VREF_14
14 VCCO - FPGA_3V3 - IO_L20P_T3_A08_D24_14
14 VCCO - FPGA_3V3 - IO_L20N_T3_A07_D23_14
14 VCCO - FPGA_3V3 - IO_L21P_T3_DQS_14
14 VCCO - FPGA_3V3 - IO_L21N_T3_DQS_A06_D22_14
14 VCCO - FPGA_3V3 - IO_L22P_T3_A05_D21_14
14 VCCO - FPGA_3V3 - IO_L22N_T3_A04_D20_14
14 VCCO - FPGA_3V3 - IO_L23P_T3_A03_D19_14
14 VCCO - FPGA_3V3 - IO_L23N_T3_A02_D18_14
14 VCCO - FPGA_3V3 - IO_L24P_T3_A01_D17_14
14 VCCO - FPGA_3V3 - IO_L24N_T3_A00_D16_14
14 VCCO - FPGA_3V3 - IO_25_14
15 VCCO - VCCO_VADJ - IO_0_15
15 VCCO - VCCO_VADJ - IO_L1P_T0_AD0P_15
15 VCCO - VCCO_VADJ - IO_L1N_T0_AD0N_15
15 VCCO - VCCO_VADJ - IO_L2P_T0_AD8P_15
15 VCCO - VCCO_VADJ - IO_L2N_T0_AD8N_15
15 VCCO - VCCO_VADJ - IO_L3P_T0_DQS_AD1P_15
15 VCCO - VCCO_VADJ - IO_L3N_T0_DQS_AD1N_15
15 VCCO - VCCO_VADJ - IO_L4P_T0_15
15 VCCO - VCCO_VADJ - IO_L4N_T0_15
15 VCCO - VCCO_VADJ - IO_L5P_T0_AD9P_15
15 VCCO - VCCO_VADJ - IO_L5N_T0_AD9N_15
15 VCCO - VCCO_VADJ - IO_L6P_T0_15
15 VCCO - VCCO_VADJ - IO_L6N_T0_VREF_15
15 VCCO - VCCO_VADJ - IO_L7P_T1_AD2P_15
15 VCCO - VCCO_VADJ - IO_L7N_T1_AD2N_15
15 VCCO - VCCO_VADJ - IO_L8P_T1_AD10P_15
15 VCCO - VCCO_VADJ - IO_L8N_T1_AD10N_15
15 VCCO - VCCO_VADJ - IO_L9P_T1_DQS_AD3P_15
15 VCCO - VCCO_VADJ - IO_L9N_T1_DQS_AD3N_15
15 VCCO - VCCO_VADJ - IO_L10P_T1_AD11P_15
15 VCCO - VCCO_VADJ - IO_L10N_T1_AD11N_15
15 VCCO - VCCO_VADJ - IO_L11P_T1_SRCC_15
15 VCCO - VCCO_VADJ - IO_L11N_T1_SRCC_15
15 VCCO - VCCO_VADJ - IO_L12P_T1_MRCC_15
15 VCCO - VCCO_VADJ - IO_L12N_T1_MRCC_15
15 VCCO - VCCO_VADJ - IO_L13P_T2_MRCC_15
15 VCCO - VCCO_VADJ - IO_L13N_T2_MRCC_15
15 VCCO - VCCO_VADJ - IO_L14P_T2_SRCC_15
15 VCCO - VCCO_VADJ - IO_L14N_T2_SRCC_15
15 VCCO - VCCO_VADJ - IO_L15P_T2_DQS_15
15 VCCO - VCCO_VADJ - IO_L15N_T2_DQS_ADV_B_15
15 VCCO - VCCO_VADJ - IO_L16P_T2_A28_15
15 VCCO - VCCO_VADJ - IO_L16N_T2_A27_15
15 VCCO - VCCO_VADJ - IO_L17P_T2_A26_15
15 VCCO - VCCO_VADJ - IO_L17N_T2_A25_15
15 VCCO - VCCO_VADJ - IO_L18P_T2_A24_15
15 VCCO - VCCO_VADJ - IO_L18N_T2_A23_15
15 VCCO - VCCO_VADJ - IO_L19P_T3_A22_15
15 VCCO - VCCO_VADJ - IO_L19N_T3_A21_VREF_15
15 VCCO - VCCO_VADJ - IO_L20P_T3_A20_15
15 VCCO - VCCO_VADJ - IO_L20N_T3_A19_15
15 VCCO - VCCO_VADJ - IO_L21P_T3_DQS_15
15 VCCO - VCCO_VADJ - IO_L21N_T3_DQS_A18_15
15 VCCO - VCCO_VADJ - IO_L22P_T3_A17_15
15 VCCO - VCCO_VADJ - IO_L22N_T3_A16_15
15 VCCO - VCCO_VADJ - IO_L23P_T3_FOE_B_15
15 VCCO - VCCO_VADJ - IO_L23N_T3_FWE_B_15
15 VCCO - VCCO_VADJ - IO_L24P_T3_RS1_15
15 VCCO - VCCO_VADJ - IO_L24N_T3_RS0_15
15 VCCO - VCCO_VADJ - IO_25_15
16 VCCO - VCCO_VADJ - IO_0_16
79