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Appendix C: Master UCF Listing
NET
DDR3_D55
NET
DDR3_D54
NET
DDR3_D53
NET
DDR3_D52
NET
DDR3_DQS6_P
NET
DDR3_DQS6_N
NET
DDR3_D51
NET
DDR3_D50
NET
DDR3_D49
NET
DDR3_D48
NET
DDR3_DM6
#NET
No Connect
NET
DDR3_D47
NET
DDR3_D46
NET
DDR3_D45
NET
DDR3_D44
NET
DDR3_DQS5_P
NET
DDR3_DQS5_N
NET
DDR3_D43
NET
DDR3_D42
NET
DDR3_D41
NET
DDR3_D40
NET
DDR3_DM5
#NET
No Connect
NET
DDR3_D39
#NET
VTTVREF
NET
DDR3_D38
NET
DDR3_D37
NET
DDR3_DQS4_P
NET
DDR3_DQS4_N
NET
DDR3_D36
NET
DDR3_D35
NET
DDR3_D34
NET
DDR3_D33
NET
DDR3_D32
NET
DDR3_DM4
#NET
No Connect
NET
SFP_MGT_CLK0_N
NET
SFP_MGT_CLK0_P
#NET
MGTRREF_213
NET
SFP_MGT_CLK1_P
NET
SFP_MGT_CLK1_N
NET
PCIE_CLK_QO_N
NET
PCIE_CLK_QO_P
#NET
MGTRREF_216
#NET
No Connect
#NET
No Connect
82
LOC = J6
| IOSTANDARD=SSTL15; # Bank
LOC = J5
| IOSTANDARD=SSTL15; # Bank
LOC = L8
| IOSTANDARD=SSTL15; # Bank
LOC = K8
| IOSTANDARD=SSTL15; # Bank
LOC = J4
| IOSTANDARD=DIFF_SSTL15; # Bank
LOC = H4
| IOSTANDARD=DIFF_SSTL15; # Bank
LOC = K7
| IOSTANDARD=SSTL15; # Bank
LOC = K6
| IOSTANDARD=SSTL15; # Bank
LOC = G4
| IOSTANDARD=SSTL15; # Bank
LOC = F4
| IOSTANDARD=SSTL15; # Bank
LOC = G5
| IOSTANDARD=SSTL15; # Bank
LOC = F5
| IOSTANDARD=SSTL15; # Bank
LOC = E5
| IOSTANDARD=SSTL15; # Bank
LOC = D5
| IOSTANDARD=SSTL15; # Bank
LOC = D4
| IOSTANDARD=SSTL15; # Bank
LOC = C4
| IOSTANDARD=SSTL15; # Bank
LOC = B5
| IOSTANDARD=DIFF_SSTL15; # Bank
LOC = A5
| IOSTANDARD=DIFF_SSTL15; # Bank
LOC = B4
| IOSTANDARD=SSTL15; # Bank
LOC = A4
| IOSTANDARD=SSTL15; # Bank
LOC = D3
| IOSTANDARD=SSTL15; # Bank
LOC = C3
| IOSTANDARD=SSTL15; # Bank
LOC = F3
| IOSTANDARD=SSTL15; # Bank
LOC = E3
| IOSTANDARD=SSTL15; # Bank
LOC = C2
| IOSTANDARD=SSTL15; # Bank
LOC = B2
| IOSTANDARD=
LOC = A3
| IOSTANDARD=SSTL15; # Bank
LOC = A2
| IOSTANDARD=SSTL15; # Bank
LOC = C1
| IOSTANDARD=DIFF_SSTL15; # Bank
LOC = B1
| IOSTANDARD=DIFF_SSTL15; # Bank
LOC = F2
| IOSTANDARD=SSTL15; # Bank
LOC = E2
| IOSTANDARD=SSTL15; # Bank
LOC = E1
| IOSTANDARD=SSTL15; # Bank
LOC = D1
| IOSTANDARD=SSTL15; # Bank
LOC = G2
| IOSTANDARD=SSTL15; # Bank
LOC = G1
| IOSTANDARD=SSTL15; # Bank
LOC = H3
| IOSTANDARD=SSTL15; # Bank
LOC = AB13 | IOSTANDARD=LVDS_25 ; # Bank 213
LOC = AA13 | IOSTANDARD=LVDS_25 ; # Bank 213
LOC = AF15
LOC = AA11 | IOSTANDARD=LVDS_25 ; # Bank 213
LOC = AB11 | IOSTANDARD=LVDS_25 ; # Bank 213
LOC = E11
| IOSTANDARD=LVDS_25 ; # Bank 216
LOC = F11
| IOSTANDARD=LVDS_25 ; # Bank 216
LOC = A15
LOC = F13
| IOSTANDARD=LVDS_25 ; # Bank 216
LOC = E13
| IOSTANDARD=LVDS_25 ; # Bank 216
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35 VCCO - FPGA_1V5 - IO_L7P_T1_AD6P_35
35 VCCO - FPGA_1V5 - IO_L7N_T1_AD6N_35
35 VCCO - FPGA_1V5 - IO_L8P_T1_AD14P_35
35 VCCO - FPGA_1V5 - IO_L8N_T1_AD14N_35
35 VCCO - FPGA_1V5 - IO_L9P_T1_DQS_AD7P_35
35 VCCO - FPGA_1V5 - IO_L9N_T1_DQS_AD7N_35
35 VCCO - FPGA_1V5 - IO_L10P_T1_AD15P_35
35 VCCO - FPGA_1V5 - IO_L10N_T1_AD15N_35
35 VCCO - FPGA_1V5 - IO_L11P_T1_SRCC_35
35 VCCO - FPGA_1V5 - IO_L11N_T1_SRCC_35
35 VCCO - FPGA_1V5 - IO_L12P_T1_MRCC_35
35 VCCO - FPGA_1V5 - IO_L12N_T1_MRCC_35
35 VCCO - FPGA_1V5 - IO_L13P_T2_MRCC_35
35 VCCO - FPGA_1V5 - IO_L13N_T2_MRCC_35
35 VCCO - FPGA_1V5 - IO_L14P_T2_SRCC_35
35 VCCO - FPGA_1V5 - IO_L14N_T2_SRCC_35
35 VCCO - FPGA_1V5 - IO_L15P_T2_DQS_35
35 VCCO - FPGA_1V5 - IO_L15N_T2_DQS_35
35 VCCO - FPGA_1V5 - IO_L16P_T2_35
35 VCCO - FPGA_1V5 - IO_L16N_T2_35
35 VCCO - FPGA_1V5 - IO_L17P_T2_35
35 VCCO - FPGA_1V5 - IO_L17N_T2_35
35 VCCO - FPGA_1V5 - IO_L18P_T2_35
35 VCCO - FPGA_1V5 - IO_L18N_T2_35
35 VCCO - FPGA_1V5 - IO_L19P_T3_35
; # Bank
35 VCCO - FPGA_1V5 - IO_L19N_T3_VREF_35
35 VCCO - FPGA_1V5 - IO_L20P_T3_35
35 VCCO - FPGA_1V5 - IO_L20N_T3_35
35 VCCO - FPGA_1V5 - IO_L21P_T3_DQS_35
35 VCCO - FPGA_1V5 - IO_L21N_T3_DQS_35
35 VCCO - FPGA_1V5 - IO_L22P_T3_35
35 VCCO - FPGA_1V5 - IO_L22N_T3_35
35 VCCO - FPGA_1V5 - IO_L23P_T3_35
35 VCCO - FPGA_1V5 - IO_L23N_T3_35
35 VCCO - FPGA_1V5 - IO_L24P_T3_35
35 VCCO - FPGA_1V5 - IO_L24N_T3_35
35 VCCO - FPGA_1V5 - IO_25_35
; # Bank 213
; # Bank 216
- MGTREFCLK0N_213
- MGTREFCLK0P_213
- MGTRREF_213
- MGTREFCLK1P_213
- MGTREFCLK1N_213
- MGTREFCLK0N_216
- MGTREFCLK0P_216
- MGTRREF_216
- MGTREFCLK1P_216
- MGTREFCLK1N_216
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
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