Xilinx AC701 User Manual page 57

Table 1-26: HPC Connections, J30 to FPGA U1 (Cont'd)
J30 FMC
Schematic Net Name
HPC Pin
A35 NC
A38 NC
A39 NC
C2 FMC1_HPC_DP0_C2M_P
C3 FMC1_HPC_DP0_C2M_N
C6 FMC1_HPC_DP0_M2C_P
C7 FMC1_HPC_DP0_M2C_N
C10 FMC1_HPC_LA06_P
C11 FMC1_HPC_LA06_N
C14 FMC1_HPC_LA10_P
C15 FMC1_HPC_LA10_N
C18 FMC1_HPC_LA14_P
C19 FMC1_HPC_LA14_N
C22 FMC1_HPC_LA18_CC_P
C23 FMC1_HPC_LA18_CC_N
C26 FMC1_HPC_LA27_P
C27 FMC1_HPC_LA27_N
C30 FMC1_HPC_IIC_SCL
C31 FMC1_HPC_IIC_SDA
C34 GND
C35 VCC12_P
C37 VCC12_P
C39 VCC3V3
E2 FMC1_HPC_HA01_CC_P
E3 FMC1_HPC_HA01_CC_N
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
U1 FPGA J30 FMC
Pin HPC Pin
NA B36 NC
NA B37 NC
NA B40 NC
AE9 D1 CTRL2_PWRGOOD
AF9 D4 FMC1_HPC_GBTCLK0_M2C_P
AE13 D5 FMC1_HPC_GBTCLK0_M2C_N
AF13 D8 FMC1_HPC_LA01_CC_P
G19 D9 FMC1_HPC_LA01_CC_N
F20 D11 FMC1_HPC_LA05_P
A17 D12 FMC1_HPC_LA05_N
A18 D14 FMC1_HPC_LA09_P
C21 D15 FMC1_HPC_LA09_N
B21 D17 FMC1_HPC_LA13_P
G20 D18 FMC1_HPC_LA13_N
G21 D20 FMC1_HPC_LA17_CC_P
F23 D21 FMC1_HPC_LA17_CC_N
E23 D23 FMC1_HPC_LA23_P
U52.19 D24 FMC1_HPC_LA23_N
U52.20 D26 FMC1_HPC_LA26_P
NA D27 FMC1_HPC_LA26_N
NA D29 FMC1_HPC_TCK_BUF
NA D30 FMC1_TDI_BUF
NA D31 FMC1_TDO_FPGA_TDI
D32 VCC3V3
D33 FMC1_HPC_TMS_BUF
D34 NC
D35 GND
D36 VCC3V3
D38 VCC3V3
D40 VCC3V3
AB21 F1 FMC1_HPC_PG_M2C
AC21 F4 FMC1_HPC_HA00_CC_P
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Feature Descriptions
Schematic Net Name
U1 FPGA
Pin
NA
NA
NA
P15
U3.27
U3.25
E17
E18
G15
F15
E16
D16
B20
A20
K21
J21
K20
J20
J24
H24
U19.13
U19.17
U19.2
NA
U19.15
NA
NA
NA
NA
NA
N17
AA19
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