Access Target Cpu Setting Status Area (Address: 4000 To 4071) - Mitsubishi Electric MELSEC Q Series User Manual

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3 SPECIFICATIONS

3.8.17 Access target CPU setting status area (Address: 4000 to 4071)

Address:
Address:
3 - 56
(c)
The following is observed when a time event monitor error occurs.
(Example) When an error occurs in time event monitor of the time/interval
event setting No. 16
 Time event monitor error (X15) turns on.
 Time event monitor error data area (address: 3201 (bit 15)) of
 The error code is stored into the time event monitor 16 error
(3) Time event monitor 1 to 16 error code (Address: 3202 to 3217)
The error code that indicates the error status is stored into the corresponding
time/interval event setting No. area.
Refer to Section 9.3 for the error code.
The setting status of the access target CPU setting can be confirmed.
Refer to Section 4.6.7 for the access target CPU setting.
(1) Access target CPU setting data (Address: 4000 to 4003)
(a)
This area stores information on whether the access target CPU setting has
been made or not.
(b)
The bit corresponding to the preset access target CPU setting No. turns on.
0: Not set
1: Set
b15
b14
b13
b12
4000
16
15
14
13
4001
32
31
30
29
4002
48
47
46
45
4003
64
63
62
61
(2) Access target CPU error data (Address: 4004 to 4007)
(a)
This area stores the access target CPU error data.
(b)
The bit corresponding to the an access target CPU setting No. of an access
target CPU error turns on.
0: No access target CPU error occurred
1: Access target CPU error occurred
b15
b14
b13
b12
4004
16
15
14
13
4005
32
31
30
29
4006
48
47
46
45
4007
64
63
62
61
the buffer memory turns on.
code area (address: 3217) of the buffer memory.
b11
b10 b9
b8 b7
b6
12
11
10
9
8
7
28
27
26
25
24
23
44
43
42
41
40
39
60
59
58
57
56
55
b11
b10 b9
b8 b7
b6
12
11
10
9
8
7
28
27
26
25
24
23
44
43
42
41
40
39
60
59
58
57
56
55
b5 b4 b3 b2 b1
b0
6
5
4
3
2
1
22
21
20
19
18
17
38
37
36
35
34
33
54
53
52
51
50
49
b5 b4 b3 b2 b1
b0
6
5
4
3
2
1
22
21
20
19
18
17
38
37
36
35
34
33
54
53
52
51
50
49
MELSEC-Q
3 - 56

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