ST STM32G4 Series Reference Manual page 2002

Advanced arm-based 32-bit mcus

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FD controller area network (FDCAN)

FDCAN Tx buffer transmission interrupt enable register

(FDCAN_TXBTIE)

Address offset: 0x00DC

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 TIE[2:0]: Transmission interrupt enable

Each Tx buffer has its own TIE bit.

0: Transmission interrupt disabled

1: Transmission interrupt enable

FDCAN Tx buffer cancellation finished interrupt enable register

(FDCAN_ TXBCIE)

Address offset: 0x00E0

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 CFIE[2:0]: Cancellation finished interrupt enable.

Each Tx buffer has its own CFIE bit.

0: Cancellation finished interrupt disabled

1: Cancellation finished interrupt enabled

RM0440 Rev 4

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