ST STM32G4 Series Reference Manual page 2024

Universal serial bus full-speed device interface (USB)
45.6 USB and USB SRAM registers
The USB peripheral registers can be divided into the following groups:
•
Common Registers: Interrupt and Control registers
• Endpoint Registers: Endpoint configuration and status
The USB SRAM registers cover:
•
Buffer Descriptor Table: Location of packet memory used to locate data buffers (see
Section 2.2: Memory organization
All register addresses are expressed as offsets with respect to the USB peripheral registers
base address, except the buffer descriptor table locations, which starts at the USB SRAM
base address offset by the value specified in the USB_BTABLE register.
Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
45.6.1 Common registers
These registers affect the general behavior of the USB peripheral defining operating mode,
interrupt handling, device address and giving access to the current frame number updated
by the host PC.
USB control register (USB_CNTR)
Address offset: 0x40
Reset value: 0x0003
15 14 13
CTR PMAOVR ERR
M M M
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Bit 15 CTRM: Correct transfer interrupt mask
Bit 14 PMAOVRM: Packet memory area over / underrun interrupt mask
Bit 13 ERRM: Error interrupt mask
Bit 12 WKUPM: Wakeup interrupt mask
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Section 1.2 on page 72
12 11 10
WKUP SUSP RESET SOF
M M M
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0: Correct Transfer (CTR) Interrupt disabled.
1: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the
USB_ISTR register is set.
0: PMAOVR Interrupt disabled.
1: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit
in the USB_ISTR register is set.
0: ERR Interrupt disabled.
1: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
0: WKUP Interrupt disabled.
1: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
to find USB SRAM base address).
for a list of abbreviations used in register descriptions.
9 8 7 6
ESOF L1REQ Res
M M M .
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RM0440 Rev 4
5 4 3
L1RESU RE F
ME SUME SUSP
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RM0440
2 1 0
LP_ PDW F
MODE N RES
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