ST STM32G4 Series Reference Manual page 2103

Advanced arm-based 32-bit mcus

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Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)

Address: 0xE004 200C

Power on reset (POR): 0x0000 0000

System reset: not affected

Access: Only 32-bit access are supported.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 DBG_I2C4_STOP: I2C4 SMBUS timeout counter stopped when core is halted

Bit 0 Reserved, must be kept at reset value.

Debug MCU APB2 freeze register (DBGMCU_APB2FZR)

Address: 0xE004 2010

Power on reset (POR): 0x0000 0000

System reset: not affected

Access: Only 32-bit access are supported.

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 DBG_HRTIM_STOP: HRTIM counter stopped when core is halted

0: The clock of the HRTIM counter is fed even if the core is halted

1: The clock of the HRTIM counter is stopped when the core is halted

Bits 25:21 Reserved, must be kept at reset value.

0: Same behavior as in normal mode

1: The I2C4 SMBus timeout is frozen

RM0440 Rev 4

Debug support (DBG)

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