Table 407. Stm32G4 Series Usb Implementation - ST STM32G4 Series Reference Manual

RM0440
45 Universal serial bus full-speed device interface (USB)
45.1 Introduction
The USB peripheral implements an interface between a full-speed USB 2.0 bus and the
APB1 bus.
USB suspend/resume are supported, which allows to stop the device clocks for low-power
consumption.
45.2 USB main features
• USB specification version 2.0 full-speed compliant
•
Configurable number of endpoints from 1 to 8
• Dedicated packet buffer memory (SRAM) of 1024 bytes
•
Cyclic redundancy check (CRC) generation/checking, Non-return-to-zero Inverted
(NRZI) encoding/decoding and bit-stuffing
•
Isochronous transfers support
•
Double-buffered bulk/isochronous endpoint support
•
USB Suspend/Resume operations
•
Frame locked clock pulse generation
• USB 2.0 Link Power Management support
•
Battery Charging Specification Revision 1.2 support
• USB connect / disconnect capability (controllable embedded pull-up resistor on
USB_DP line)
45.3 USB implementation
Table 407
Number of endpoints
Size of dedicated packet buffer memory SRAM
Dedicated packet buffer memory SRAM access scheme
USB 2.0 Link Power Management (LPM) support
Battery Charging Detection (BCD) support
Embedded pull-up resistor on USB_DP line
1. X= supported
describes the USB implementation in the devices.

Table 407. STM32G4 Series USB implementation

USB features
Universal serial bus full-speed device interface (USB)
(1)
RM0440 Rev 4
USB
8
1024 bytes
2 x 16 bits / word
X
X
X
2009/2126
2041