ST STM32G4 Series Reference Manual page 1993

RM0440
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 LSE[3:0]: List size extended
0: No extended message ID filter
1 to 8: Number of extended message ID filter elements
>8: Values greater than 8 are interpreted as 8.
These are protected write (P) bits, which means that write access by the bits is possible only
when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
Bits 23:21 Reserved, must be kept at reset value.
Bits 20:16 LSS[4:0]: List size standard
0: No standard message ID filter
1 to 28: Number of standard message ID filter elements
>28: Values greater than 28 are interpreted as 28.
These are protected write (P) bits, which means that write access by the bits is possible only
when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 F0OM: FIFO 0 operation mode (overwrite or blocking)
This is protected write (P) bits, which means that write access by the bits is possible only
when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
Bit 8 F1OM: FIFO 1 operation mode (overwrite or blocking)
This is a protected write (P) bits, which means that write access by the bits is possible only
when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 ANFS[1:0]: Accept Non-matching frames standard
Defines how received messages with 11-bit IDs that do not match any element of the filter list
are treated.
00: Accept in Rx FIFO 0
01: Accept in Rx FIFO 1
10: Reject
11: Reject
These are protected write (P) bits, which means that write access by the bits is possible only
when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
Bits 3:2 ANFE[1:0]: Accept non-matching frames extended
Defines how received messages with 29-bit IDs that do not match any element of the filter list
are treated.
00: Accept in Rx FIFO 0
01: Accept in Rx FIFO 1
10: Reject
11: Reject
These are protected write (P) bits, which means that write access by the bits is possible only
when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
FD controller area network (FDCAN)
RM0440 Rev 4 1993/2126
2008