ST STM32G4 Series Reference Manual page 2000

Advanced arm-based 32-bit mcus

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FD controller area network (FDCAN)

FDCAN Tx buffer add request register (FDCAN_TXBAR)

Address offset: 0x00CC

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 AR[2:0]: Add request

Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request

bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple

Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset

immediately, else the bits remain set until the Tx scan process has completed.

0: No transmission request added

1: Transmission requested added.

If an add request is applied for a Tx buffer with pending transmission request

(corresponding TXBRP bit already set), the request is ignored.

FDCAN Tx buffer cancellation request register (FDCAN_TXBCR)

Address offset: 0x00D0

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 CR[2:0]: Cancellation request

Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit;

writing a 0 has no impact.

This enables the Host to set cancellation requests for multiple Tx buffers with one write to

TXBCR. The bits remain set until the corresponding TXBRP bit is reset.

0: No cancellation pending

1: Cancellation pending

RM0440 Rev 4

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