Figure 672. Packet Buffer Areas With Examples Of Buffer Description Table Locations - ST STM32G4 Series Reference Manual

Universal serial bus full-speed device interface (USB)
back-to-back accesses. The USB peripheral logic uses a dedicated clock. The frequency of
this dedicated clock is fixed by the requirements of the USB standard at 48 MHz, and this
can be different from the clock used for the interface to the APB1 bus. Different clock
configurations are possible where the APB1 clock frequency can be higher or lower than the
USB peripheral one.
Note: For USB throughput and system performance reasons during USB active bus connection it
is recommended to run APB1 clock no lower than 48 MHz.
Each endpoint is associated with two packet buffers (usually one for transmission and the
other one for reception). Buffers can be placed anywhere inside the packet memory
because their location and size is specified in a buffer description table, which is also
located in the packet memory at the address indicated by the USB_BTABLE register. Each
table entry is associated to an endpoint register and it is composed of four 16-bit half-words
so that table start address must always be aligned to an 8-byte boundary (the lowest three
bits of USB_BTABLE register are always "000"). Buffer descriptor table entries are
described in the
is neither an Isochronous nor a double-buffered bulk, only one packet buffer is required (the
one related to the supported transfer direction). Other table locations related to unsupported
transfer directions or unused endpoints, are available to the user. Isochronous and double-
buffered bulk endpoints have special handling of packet buffers (Refer to
Isochronous transfers
relationship between buffer description table entries and packet buffer areas is depicted in
Figure 672.

Figure 672. Packet buffer areas with examples of buffer description table locations

0001_1110 (1E)
0001_1100 (1C)
0001_1010 (1A)
0001_1000 (18)
0001_0110 (16)
0001_0100 (14)
0001_0010 (12)
0001_0000 (10)
0000_1110 (0E)
0000_1100 (0C)
0000_1010 (0A)
0000_1000 (08)
0000_0110 (06)
0000_0100 (04)
0000_0010 (02)
0000_0000 (00)
2014/2126
Section 45.6.2: Buffer descriptor
and Section 45.5.3: Double-buffered endpoints
COUNT3_TX_1
ADDR3_TX_1
COUNT3_TX_0
ADDR3_TX_0
COUNT2_RX_1
ADDR2_RX_1
COUNT2_RX_0
ADDR2_RX_0
COUNT1_RX
ADDR1_RX
COUNT1_TX
ADDR1_TX
COUNT0_RX
ADDR0_RX
COUNT0_TX
ADDR0_TX
Buffer description table locations
table. If an endpoint is unidirectional and it
RM0440 Rev 4
Section 45.5.4:
respectively). The
Buffer for
double-buffered
IN Endpoint 3
Buffer for
double-buffered
OUT Endpoint 2
Transmission
buffer for
single-buffered
Endpoint 1
Reception buffer
for
Endpoint 0
Transmission
buffer for
Endpoint 0
Packet buffers
MSv32129V1
RM0440