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15.3 CLDO
Table 27. CLDO Specifications
Specification
Input supply voltage, V
in
Output current
Output voltage, V
o
Dropout voltage
Output voltage DC
accuracy
Quiescent current
Line regulation
Load regulation
Leakage current
PSRR
Start-up time of PMU
LDO turn-on time
External output capacitor,
C
o
External input capacitor
1. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.
Document Number: 002-14826 Rev. *G
PRELIMINARY
Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement must be met
under maximum load.
–
Programmable in 10 mV steps. Default = 1.2.V.
At max. load.
Includes line/load regulation.
No load.
200 mA load.
V
from (V
+ 0.15V) to 1.5V, maximum load.
in
o
Load from 1 mA to 300 mA.
Power down.
Bypass mode.
@1 kHz, Vin ≥ 1.35V, C
= 4.7 µF.
o
VIO up and steady. Time from the REG_ON rising edge to the CLDO
reaching 1.2V.
LDO turn-on time when the rest of the chip is up.
Total ESR: 5 mΩ–240 mΩ.
Only use an external input capacitor at the LDO_VDD1P5 pin if it is not
supplied from the CBUCK output.
Notes
CYW43903
Min.
Typ.
Max.
Units
1.3
1.35
1.5
V
0.2
–
350
mA
0.95
1.2
1.26
V
–
–
150
mV
–4
–
+4
%
–
26
–
µA
–
2.48
–
mA
–
–
5
mV/V
–
0.02
0.05
mV/mA
–
10
40
µA
–
2
6
µA
20
–
dB
–
–
700
µs
–
140
180
µs
4.7
–
µF
1
3.76
–
1
2.2
µF
Page 51 of 65
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