Xilinx Virtex-7 FPGA VC7203 Getting Started Manual page 17

Starting the SuperClock-2 Module
The IBERT demonstration designs use an integrated VIO core to control the clocks on the
SuperClock-2 module. The SuperClock-2 module features two clock-source components:
• Always-on Si570 crystal oscillator
• Si5368 jitter-attenuating clock multiplier.
Outputs from either device can be used to drive the transceiver reference clocks.
To start the SuperClock-2 module:
1. The Vivado Design Suite Hardware window shows the System ACE controller and the
XC7VX485T device. The XC7VX485T device is reported as programmed. In the Hardware
Device Properties window, enter the file path to the Q115 Probes file
(vc7203_ibert_q115_debug_nets.ltx) in the extracted IBERT files from the SD
card (Figure
X-Ref Target - Figure 1-13
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
1-13).
Figure 1-13: Adding the Probes File
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Chapter 1: VC7203 IBERT Getting Started Guide
17
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