Xilinx Virtex-7 FPGA VC7203 Getting Started Manual page 32

9. In the Clock Settings tab, select DIFF SSTL15 for the I/O Standard, enter E19 for P Package
Pin and E18 for N Package Pin (the FPGA pins that the system clock connects to), and
make sure the Frequency is set to 200.00
Products window opens. Leave the defaults unchanged, and press Generate.
X-Ref Target - Figure 1-26
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
Chapter 1: VC7203 IBERT Getting Started Guide
(Figure
Figure 1-26: Customize IP - Clock Settings
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1-26). Press OK. A Generate Output
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