Xilinx Virtex-7 FPGA VC7203 Getting Started Manual page 23

Viewing GTX Transceiver Operation
After completing
configured and running. The status and test settings are displayed on the Links tab in the
Links window shown in
Note the line rate and error count:
• The line rate for all four GTX transceivers is 12.5 Gb/s (see Status in
• Verify that there are no bit errors.
X-Ref Target - Figure 1-19
In Case of RX Bit Errors
If there are initial bit errors after linking, or as a result of changing the TX or RX pattern, click
the respective BERT Reset button to zero the count.
If the MGT Link Status shows No Link for one or more transceivers:
• Make sure the blue elastomer seal is connected to the bottom of the BullsEye cable and
the cable is firmly connected and flush on the board.
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
step 6 in Starting the SuperClock-2
Figure 1-19.
Figure 1-19: Serial I/O Analyzer Links
www.xilinx.com
Chapter 1: VC7203 IBERT Getting Started Guide
Module, the IBERT demonstration is
Figure 1-19).
23
Send Feedback