Xilinx Virtex-7 FPGA VC7203 Getting Started Manual page 7

• Probe files
vc7203_ibert_113_debug_nets.ltx
vc7203_ibert_114_debug_nets.ltx
vc7203_ibert_115_debug_nets.ltx
vc7203_ibert_116_debug_nets.ltx
vc7203_ibert_117_debug_nets.ltx
vc7203_ibert_118_debug_nets.ltx
vc7203_ibert_119_debug_nets.ltx
• Tcl scripts
add_scm2.tcl
setup_scm2_156_25.tcl
The Tcl scripts are used to help merge the IBERT and SuperClock-2 source code (described
in Creating the GTX IBERT Core, page
156.25 MHz (described in
are used by Vivado design tools to properly load the SuperClock-2 VIO core.
To copy the files from the Secure Digital memory card:
1. Connect the Secure Digital memory card to the host computer.
2. Locate the file rdf0272-vc7203-ibert-2015-1.zip on the Secure Digital memory
card.
3. Unzip the files to a working directory on the host computer.
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
Chapter 1: VC7203 IBERT Getting Started Guide
26) and to set up the SuperClock-2 module to run at
Setting Up the Vivado Design Suite, page
www.xilinx.com
14). The debug probes
7
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