Xilinx Virtex-7 FPGA VC7203 Getting Started Manual page 34

11. In the new window, select Tools > Run Tcl Script. In the Run Script window, navigate to
add_scm2.tcl in the extracted files and press OK. The SuperClock-2 Module Design
Sources and Constraints are automatically added to the example design
X-Ref Target - Figure 1-28
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
Figure 1-28: Sources after Running add_scm2.tcl
www.xilinx.com
Chapter 1: VC7203 IBERT Getting Started Guide
(Figure 1-28).
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