Extracting The Project Files - Xilinx Virtex-7 FPGA VC7203 Getting Started Manual

1. Move all jumpers and switches to their default positions. The default jumper and switch
positions are listed in VC7203 Virtex-7 FPGA GTX Transceiver Characterization Board
User Guide (UG957)
2. Install the GTX transceiver power module by plugging it into connectors J66 and J97.
3. Install the SuperClock-2 module:
a. Align the three metal standoffs on the bottom side of the module with the three
mounting holes in the SUPERCLOCK-2 MODULE interface of the VC7203 board.
b. Using three 4-40 x 0.25 inch screws, firmly screw down the module from the bottom
of the VC7203 board.
c. On the SuperClock-2 module, place a jumper across pins 2–3 (2V5) of the CONTROL
VOLTAGE header, J18, and place another jumper across Si570 INH header J11.
d. Screw down a 50Ω SMA terminator onto each of the six unused Si5368 clock output
SMA connectors: J7, J8, J12, J15, J16 and J17.

Extracting the Project Files

The Vivado project files required to run the IBERT demonstrations are located in
rdf0272-vc7203-ibert-2015-1.zip on the SD card provided with the VC7203 board.
They are also available online at the
documentation
The ZIP file contains these files:
• BIT files
vc7203_ibert_q113_152.bit
vc7203_ibert_q114_152.bit
vc7203_ibert_q115_152.bit
vc7203_ibert_q116_152.bit
vc7203_ibert_q117_152.bit
vc7203_ibert_q118_152.bit
vc7203_ibert_q119_152.bit
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
[Ref 1].
Virtex-7 FPGA VC7203 Characterization Kit
website.
www.xilinx.com
Chapter 1: VC7203 IBERT Getting Started Guide
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