Xilinx Virtex-7 FPGA VC7203 Getting Started Manual page 11

GTX Transceiver Clock Connections
See Figure 1-2
clock inputs. Connect these cables to the SuperClock-2 module as follows:
• CLK1_P coax cable → SMA connector J5 (CLKOUT1_P) on the SuperClock-2 module
• CLK1_N coax cable → SMA connector J6 (CLKOUT1_N) on the SuperClock-2 module
Any one of the five differential outputs from the SuperClock-2 module can be used to source
Note:
the GTX reference clock. CLKOUT1_P and CLKOUT1_N are used here as an example.
GTX TX/RX Loopback Connections
See Figure 1-2
(RX0, RX1, RX2 and RX3) and the four transmitters (TX0, TX1, TX2 and TX3). Use eight SMA
female-to-female (F-F) adapters
shown in Figure 1-7
• TX0_P → SMA F-F Adapter → RX0_P
• TX0_N → SMA F-F Adapter → RX0_N
• TX1_P → SMA F-F Adapter → RX1_P
• TX1_N → SMA F-F Adapter → RX1_N
• TX2_P → SMA F-F Adapter → RX2_P
• TX2_N → SMA F-F Adapter → RX2_N
• TX3_P → SMA F-F Adapter → RX3_P
• TX3_N → SMA F-F Adapter → RX3_N
To ensure good connectivity, it is recommended that the adapters be secured with a wrench;
Note:
however, do not over-tighten the SMAs.
X-Ref Target - Figure 1-6
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
to identify the P and N coax cables that are connected to the CLK1 reference
to identify the P and N coax cables that are connected to the four receivers
(Figure
and detailed here:
Figure 1-6: SMA F-F Adapter
www.xilinx.com
Chapter 1: VC7203 IBERT Getting Started Guide
1-6), to connect the transmit and receive cables as
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