Xilinx Virtex-7 FPGA VC7203 Getting Started Manual page 35

12. The SuperClock-2 source code now needs to be added to the example IBERT wrapper.
Double-click example_ibert_7series_gtx_0 in Design Sources to open the Verilog code.
Add the top level ports from top_scm2.v to the module declaration and instantiate the
top_scm2 module in the example IBERT wrapper
X-Ref Target - Figure 1-29
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
Figure 1-29: SuperClock-2 in the Example IBERT Wrapper
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Chapter 1: VC7203 IBERT Getting Started Guide
(Figure 1-29). Click File > Save File.
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