Creating The Gtx Ibert Core - Xilinx Virtex-7 FPGA VC7203 Getting Started Manual

Creating the GTX IBERT Core

Vivado Design Suite 2015.1 is required to rebuild the designs shown here.
This section provides a procedure to create a single Quad GTX IBERT core with integrated
SuperClock-2 controller. The procedure assumes Quad 113 and 12.5 Gb/s line rate, but
cores for any of the GTX Quads with any supported line rate can be created following the
same series of steps.
For more details on generating IBERT cores, refer to Vivado Design Suite User Guide:
Programming and Debugging (UG908)
1. Start the Vivado Design Suite.
2. In the Vivado design tools window, click the Manage IP icon (highlighted in
then select New IP Location.
X-Ref Target - Figure 1-20
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
[Ref
Figure 1-20: Vivado Design Suite Initial Window
www.xilinx.com
Chapter 1: VC7203 IBERT Getting Started Guide
3].
Figure 1-20),
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