Xilinx Virtex-7 FPGA VC7203 Getting Started Manual page 38

16. When the Synthesized Design opens, select dbg_hub in the Netlist window, then select
the Debug Core Options tab in the Cell Properties window and change
C_USER_SCAN_CHAIN* to 3
X-Ref Target - Figure 1-33
17. In the Flow Navigator under Program and Debug, click Generate Bitstream
A window pops up asking if it is okay to launch implementation. Click Yes.
X-Ref Target - Figure 1-34
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
Chapter 1: VC7203 IBERT Getting Started Guide
(Figure 1-33). Click File > Save Constraints.
Figure 1-33: Dbg_hub Debug Core Options
Figure 1-34: Generate Bitstream
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(Figure 1-34).
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