Xilinx Virtex-7 FPGA VC7203 Getting Started Manual page 20

4. To view the SuperClock 2 settings in the VIO core, select the probe signal from the
Debug Probes window and drag it to the VIO window. For example, the frequencies,
ROM addresses, and start signals are selected from
The ROM address values for the Si5368 and Si570 devices (that is, si5368_addr[6:0] and
Note:
si570_addr[6:0]) are preset to 60 to produce an output frequency of 156.250 MHz. Entering a
different ROM address changes the reference clock(s) frequency. The complete list of
pre-programmed SuperClock-2 frequencies and their associated ROM addresses is provided in
Table 1-2.
X-Ref Target - Figure 1-16
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
Figure 1-16: SuperClock-2 Module VIO Core
www.xilinx.com
Chapter 1: VC7203 IBERT Getting Started Guide
Figure 1-16.
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