Chapter 2: Board Components
Memory
Table 2–35. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board
Reference
U27.7
Dedicated CMOS I/O bit 73 when
LCD_HSMB_SEL is set to a logic 1.
U27.12
Dedicated CMOS I/O bit 74 when
LCD_HSMB_SEL is set to a logic 1.
U27.9
Dedicated CMOS I/O bit 75 when
LCD_HSMB_SEL is set to a logic 1.
J1.155
LVDS or CMOS clock out 2 or CMOS bit 76
J1.156
LVDS or CMOS clock in 2 or CMOS bit 77
J1.157
LVDS or CMOS clock out 2 or CMOS bit 77
J1.158
LVDS or CMOS clock in 2n or CMOS bit 79
J1.160
HSMC port B presence detect LED
J18
To control the HSMB_D[65:75] via the FPGA,
the shunt should be removed from this jumper,
or the FPGA must drive a logic 1.
Note to
Table
2–35:
(1) Board references J1.1 to J1.32 are not connected.
Table 2–36
information.
Table 2–36. HSMC Connector Component Reference and Manufacturing Information
Board Reference
J1 and J2
HSMC, custom version of QSH-DP
family high-speed socket.
Memory
This section describes the board's memory interface support and also their signal
names, types, and connectivity relative to the Cyclone III LS device. The board has the
following memory interfaces:
■
■
■
■
f
For more information about the memory interfaces, refer to the following documents:
■
■
© October 2009 Altera Corporation
Description
lists the HSMC connector component reference and manufacturing
Description
DDR2
SSRAM
Flash
EEPROM
AN 438: Constraining and Analyzing Timing for External Memory Interfaces in Stratix
IV, Stratix III, and Cyclone III
AN 445: Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces in
Cyclone III
Devices.
Schematic Signal
Name
LCD_HSMB_D73
LCD_HSMB_D74
LCD_HSMB_D75
HSMB_CLKOUT_P2
HSMB_CLKIN_P2
HSMB_CLKOUT_N2
HSMB_CLKIN_N2
HSMB_PRSNTn
LCD_HSMB_SEL
Manufacturing
Manufacturer
Part Number
Samtec
ASP-122953-01
Devices.
Cyclone III LS FPGA Development Board Reference Manual
(1)
Cyclone III LS
Device
I/O Standard
Pin Number
W4
W6
W7
2.5-V
T6
T2
T5
T1
—
D20
1.8-V
Manufacturer
Website
www.samtec.com
2–35
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