Altera Cyclone III LS Reference Manual page 34

2–26
Table 2–29. LCD Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
J19.4 LCD chip select (LCD_CSn) when
LCD_HSMB_SEL is set to a logic 0.
J19.11 LCD data bus bit 4 (LCD_DATA4) when
LCD_HSMB_SEL is set to a logic 0.
J19.5 LCD write enable (LCD_WEn) when
LCD_HSMB_SEL is set to a logic 0.
J19.14 LCD data bus bit 7 (LCD_DATA7) when
LCD_HSMB_SEL is set to a logic 0.
J19.12 LCD data bus bit 5 (LCD_DATA5) when
LCD_HSMB_SEL is set to a logic 0.
J19.13 LCD data bus bit 6 (LCD_DATA6) when
LCD_HSMB_SEL is set to a logic 0.
J19.4 LCD data or command select (LCD_D_Cn) when
LCD_HSMB_SEL is set to a logic 0.
J19.7 LCD data bus bit 0 (LCD_DATA0) when
LCD_HSMB_SEL is set to a logic 0.
J19.8 LCD data bus bit 1 (LCD_DATA1) when
LCD_HSMB_SEL is set to a logic 0.
J19.10 LCD data bus bit 3 (LCD_DATA3) when
LCD_HSMB_SEL is set to a logic 0.
J19.9 LCD data bus bit 2 (LCD_DATA2) when
LCD_HSMB_SEL is set to a logic 0.
J18 To control the LCD via the FPGA, a shunt should
be placed on this jumper, or the FPGA must drive
a logic 0.
Table 2–30
sheet.
f
For more information such as timing, character maps, interface guidelines, and other
related documentation, visit www.lumex.com.
Table 2–30. LCD Pin Definitions and Functions (Part 1 of 2)
Number
Cyclone III LS FPGA Development Board Reference Manual
Description
shows the LCD pin definitions, and is an excerpt from the Lumex data
Pin
Symbol
1 V
DD
2 V
SS
3 V
0
4 RS
Schematic Signal
Name
LCD_HSMB_D[65]
LCD_HSMB_D[66]
LCD_HSMB_D[67]
LCD_HSMB_D[68]
LCD_HSMB_D[69]
LCD_HSMB_D[70]
LCD_HSMB_D[71]
LCD_HSMB_D[72]
LCD_HSMB_D[73]
LCD_HSMB_D[74]
LCD_HSMB_D[75]
LCD_HSMB_SEL
Level
— Power supply
—
—
H/L Register select signal
H: Data input
L: Instruction input
Chapter 2: Board Components
General User Input/Output
Cyclone III LS
I/O Device
Standard Pin Number
P1
AE4
J4
AE1
AF1
AD2
2.5-V
L1
V5
W4
W6
W7
D20
1.8-V
Function
5 V
GND (0 V)
For LCD drive
© October 2009 Altera Corporation