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2–40
Table 2–40. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board Reference
U14.A1
Address bus
U14.B11
Address bus
U14.C10
Address bus
U14.P2
Address bus
U14.J10
Data bus
U14.J11
Data bus
U14.K10
Data bus
U14.K11
Data bus
U14.L10
Data bus
U14.L11
Data bus
U14.M10
Data bus
U14.M11
Data bus
U14.D10
Data bus
U14.D11
Data bus
U14.E10
Data bus
U14.E11
Data bus
U14.F10
Data bus
U14.F11
Data bus
U14.G10
Data bus
U14.G11
Data bus
U14.D1
Data bus
U14.D2
Data bus
U14.E1
Data bus
U14.E2
Data bus
U14.F1
Data bus
U14.F2
Data bus
U14.G1
Data bus
U14.G2
Data bus
U14.J1
Data bus
U14.J2
Data bus
U14.K1
Data bus
U14.K2
Data bus
U14.L1
Data bus
U14.L2
Data bus
U14.M1
Data bus
U14.M2
Data bus
U14.A8
Address status controller
U14.B9
Address status processor
U14.A9
Address valid
Cyclone III LS FPGA Development Board Reference Manual
Description
Schematic Signal Name
FSM_A22
FSM_A23
FSM_A24
FSM_A25
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
FSM_D16
FSM_D17
FSM_D18
FSM_D19
FSM_D20
FSM_D21
FSM_D22
FSM_D23
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
FSM_D30
FSM_D31
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
Chapter 2: Board Components
Cyclone III LS Device
I/O Standard
Pin Number
AB16
AE13
AG11
AE9
AH9
AH24
AF25
AE5
AB11
AD24
AF9
AE7
AE23
AF15
AD17
AF20
AH25
AE18
AD6
2.5-V
AG20
AH20
AH18
AF8
AE20
AB19
AB10
AC17
AD10
AG9
AE21
AD22
AH23
AG5
AB9
AD9
AD16
AH19
AB18
AB20
© October 2009 Altera Corporation
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