Development Board Block Diagram; Handling The Board - Altera Cyclone III LS Reference Manual

1–4

Development Board Block Diagram

Figure 1–1
Figure 1–1. Cyclone III LS FPGA Development Board Block Diagram
USB
Embedded
2.0
Programmable Oscillator
100 M, 125 M, 156.25 M,
SMA (LVPECL)
2x16 LCD

Handling the Board

When handling the board, it is important to observe the following static discharge
precaution:
c
Without proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
Cyclone III LS FPGA Development Board Reference Manual
shows the block diagram of the Cyclone III LS FPGA development board.
66.6 MHz
512 Mbyte
DDR2 (x16)
Z Z
Blaster
JTAG Chain
x74
CLKIN x3
CLKOUT x3
x2 CLK IN
(LVPECL)
x16
x11
Gigabit
Ethernet
PHY (RGMII)
EEPROM 512 Mbyte
2 DDR2 (x16)
(32 Kbit I C)
EP3CLS200F780
Migratable to
EP3CLS70F780
x13
Push-button
Switches,
DIP Switches,
CPLD
LEDs
Anti-Tamper
Example
Design
Chapter 1: Overview
Development Board Block Diagram
x74
CLKIN x2
CLKOUT x2
Clock_SMA
SMA
x26 ADDR
x32 DATA
64 Mbyte 2 Mbyte
Flash SSRAM
© October 2009 Altera Corporation