Altera Cyclone III LS Reference Manual page 17

Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 4)
Schematic Signal Name
FSM_D16
FSM_D17
FSM_D18
FSM_D19
FSM_D20
FSM_D21
FSM_D22
FSM_D23
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
FSM_D30
FSM_D31
HEARTBEAT
HSMA_PRSNTn
HSMB_PRSNTn
JTAG_AT_SEL
JTAG_SECURE
M2Z_CONF_DONE
M2Z_D0
M2Z_DCLK
M2Z_nCONFIG
M2Z_nSTATUS
MAX2_BEn0
MAX2_BEn1
MAX2_BEn2
MAX2_BEn3
MAX2_CLK
MAX2_CSn
MAX2_OEn
MAX2_WEn
MAX_CONF_DONE
MAX_DIP0
MAX_DIP1
AT_ACTIVE
© October 2009 Altera Corporation
EPM2210
I/O Standard Pin Number
N9
T8
T9
R9
P9
T10
M10
T11
N10
R11
P10
T12
M11
R12
N11
T13
M1
J16
J13
2.5-V K16
R5
R13
T15
N12
R14
M12
F5
F2
F6
F1
E1
E2
F3
F4
E15
F16
G13
F15
EP3CLS200
Pin Number
AH20 FSM bus data
AH18 FSM bus data
AF8 FSM bus data
AE20 FSM bus data
AB19 FSM bus data
AB10 FSM bus data
AC17 FSM bus data
AD10 FSM bus data
AG9 FSM bus data
AE21 FSM bus data
AD22 FSM bus data
AH23 FSM bus data
AG5 FSM bus data
AB9 FSM bus data
AD9 FSM bus data
AD16 FSM bus data
AH7 Anti-Tamper FPGA general I/O
— HSMC port A present
— HSMC port B present
— Jumper OFF (default): Select JTAG chain
Jumper ON: MAX II controls FPGA JTAG
— DIP - JTAG security mode ON/OFF
— On-board USB-Blaster FPGA configuration done
— On-board USB-Blaster FPGA configuration data
— On-board USB-Blaster FPGA configuration clock
— On-board USB-Blaster FPGA configuration active
— On-board USB-Blaster FPGA configuration ready
AG21 FSM bus MAX II byte enable 0
AF11 FSM bus MAX II byte enable 1
AG2 FSM bus MAX II byte enable 2
AC16 FSM bus MAX II byte enable 3
AE24 FSM bus MAX II clock
AG4 FSM bus MAX II chip select
AC10 FSM bus MAX II output enable
AA8 FSM bus MAX II write enable
— FPGA configuration done LED
— DIP - Anti-Tamper example design
— DIP - Anti-Tamper example design
— DIP - Anti-Tamper example design ON/OFF
Cyclone III LS FPGA Development Board Reference Manual
Description
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