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Cyclone III 3C120 Development Board Reference Manual 101 Innovation Drive Document Version: San Jose, CA 95134 Document Date: March 2009 www.altera.com Arrow.com. Downloaded from...
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Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation.
® enable the inter-operability of the Cyclone III device, allowing application-specific customization of the development board. For more information about the Altera Video and Image Processing Suite MegaCore functions, refer to the Video and Image Processing Suite User Guide.
■ Quartus II development software’s power optimization tools Board Component Blocks The board features the following major component blocks: ■ 780-pin Altera Cyclone III EP3C120 FPGA in a BGA package 119K logic elements (LEs) ■ 3,888 Kbits of memory ■...
2.5-V LVDS (1 single-ended, 2 differential) Device I/O total: 491 For additional information about Altera devices, go to www.altera.com/products/devices. I/O and Clocking Resources This section lists specific I/O and clocking resources available with the EP3C120F780C7 device, which is the largest of the Cyclone III devices.
65 I/O 73 I/O 71 I/O MAX II CPLD The board utilizes an Altera MAX II CPLD for the following purposes: ■ Power-up configuration of the FPGA from flash memory Embedded USB-Blaster core for USB-based configuration of the FPGA ■...
Note to Table 2–5: (1) For more information about the MAX II pin-out, refer to the Altera website at www.altera.com/literature/lit-dp.jsp. Table 2–6 lists the MAX II component reference and manufacturing information. Table 2–6. MAX II Component Reference and Manufacturing Information...
USB 2.0 interface and the Quartus II Programmer ’s JTAG mode. The development kit implements the Altera PFL megafunction for flash programming. The PFL is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash device.
Samtec ASP-122953-01. The HSM connector interface also allows for JTAG, SMBus, clock outputs and inputs, as well as power for compatible HSMC daughter cards. The HSMC is an Altera-developed specification, which allows users to expand the functionality of the development board through the addition of HSMC daughter cards.
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Clocks are terminated using a single 100Ω resistor across each P/N pair. Altera recommends using the 50Ω OCT on the FPGA for data, and the 10 mA setting for the address and control pins. The DDR2 devices should use the reduced drive strength setting available as a register option.
The SRAM devices are part of a shared bus with connectivity to the MAX II CPLD as well as the flash memory, which is called the FSM bus. All three devices use 1.8-V CMOS signaling. Altera recommends using the 50-Ω OCT setting on the FPGA and the one-half drive setting on the SRAM.
The flash device is part of a shared bus with connectivity to the MAX II CPLD as well as the SRAM memory, which is called the FSM bus. All three devices use 1.8-V CMOS signaling. Altera recommends using the 50-Ω OCT setting on the FPGA. The flash does not have a drive strength setting.
Non-technical support (General) Email nacomp@altera.com (Software Licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions This document uses the typographic conventions shown in the following table. Visual Cue Meaning...
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