Altera Cyclone III LS Reference Manual page 15

Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Table 2–5
Controller. The signal names and functions are relative to the MAX II device (U22).
Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 1 of 4)
Schematic Signal Name
CLK50_EN
CLK66_EN
CLK_CONFIG
CLK_ENABLE
CLK_SEL
CLKIN_50
CPU_RESETn
CRC_ERROR
CRC_ERROR_MAX
CRC_ERROR_PB
CRC_LATCH_SIG
FLASH_ADVn
FLASH_CEn
FLASH_CLK
FLASH_OEn
FLASH_RDYBSYn
FLASH_RESETn
FLASH_WEn
FPGA_CONF_DONE
FPGA_CONFIG_D0
FPGA_DCLK
FPGA_EPM2210_TCK
FPGA_EPM2210_TDI
FPGA_EPM2210_TDO
FPGA_EPM2210_TMS
FPGA_INIT_DONE
FPGA_nCONFIG
FPGA_nSTATUS
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
FSM_A0
FSM_A1
FSM_A2
© October 2009 Altera Corporation
lists the I/O signals present on the MAX II CPLD EPM2210 System
EPM2210
I/O Standard Pin Number
H16
H13
J12
N7
T5
J5
R8
K5
K12
R16
K4
B3
E6
C6
B4
D6
C4
A4
2.5-V
J1
D3
H4
C15
E13
E14
C14
N5
T2
H3
P14
P15
M14
N13
C13
B16
C12
EP3CLS200
Pin Number
— 50 MHz oscillator enable
— 66.6 MHz oscillator enable
— 100 MHz configuration clock input
— DIP - clock oscillator enable
— DIP - clock select SMA or oscillator
— 50 MHz clock input
W27 FPGA reset push-button switch
P26 FPGA CRC error
— CRC error LED
— CRC error insert push-button switch
AF5 Anti-Tamper FPGA general I/O
AF18 FSM bus flash memory address valid
AH22 FSM bus flash memory chip enable
AH6 FSM bus flash memory clock
AD7 FSM bus flash memory output enable
V4 FSM bus flash memory ready
AH5 FSM bus flash memory reset
AH17 FSM bus flash memory write enable
P22 FPGA configuration done
K1 FPGA configuration data
L6 FPGA configuration clock
— FPGA JTAG TCK
— FPGA JTAG TDI
— FPGA JTAG TDO
— FPGA JTAG TMS
P27 FPGA INIT_DONE signal
M3 FPGA configuration active
M1 FPGA configuration ready
— Anti-Tamper example design JTAG connector TCK
— Anti-Tamper example design JTAG connector TDI
— Anti-Tamper example design JTAG connector
TDO
— Anti-Tamper example design JTAG connector
TMS
AG6 FSM bus address
AD14 FSM bus address
AA17 FSM bus address
Cyclone III LS FPGA Development Board Reference Manual
Description
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