Cyclone Iii Ls Fpga Clock Outputs - Altera Cyclone III LS Reference Manual

2–22
Table 2–20. Cyclone III LS FPGA Development Board Clock Inputs (Part 2 of 2)
Schematic Signal
Source Name
Samtec HSMC
HSMA_CLKIN_P1
HSMA_CLKIN_N1
Samtec HSMC
HSMA_CLKIN_P2
HSMA_CLKIN_N2
Samtec HSMC
HSMB_CLKIN0
Samtec HSMC
HSMB_CLKIN_P2
HSMB_CLKIN_N2
Note to Table 2–20:
(1) CDCM61001 has a default frequency of 125 MHz, but can also be set to frequencies of 100 MHz, 150 MHz, and 156.25 MHz by the MAX II CPLD
EPM2210 System Controller..

Cyclone III LS FPGA Clock Outputs

Figure 2–7
Figure 2–7. Cyclone III LS FPGA Development Board Clock Outputs
7 6 5 4 3 2 1 0
HSMB_CLKOUT_P[2]/N[2]
(LVDS)
Cyclone III LS FPGA Development Board Reference Manual
Cyclone III LS
Device Pin Number
AG16
AH16
T27
T28
B13
T2
T1
shows the Cyclone III LS FPGA development board clock outputs.
HSMB
Bank 8
PLL 3
EP3CLS200F780
Migratable to
EP3CLS70F780
PLL 1
Bank 3
I/O
Standard
LVTTL inputs from the installed HSMC port A
LVTTL cable or board. Can also support LVDS inputs
when the termination resistor is installed.
LVTTL input from the installed HSMC port A
LVTTL cable or board. Can also support LVDS inputs.
when the termination resistor is installed
Single-ended input from the installed HSMC
LVTTL
port B cable or board.
LVTTL input from the installed HSMC port B
LVTTL cable or board. Can also support LVDS inputs
when the termination resistor is installed.
7 6 5 4 3 2 1 0
HSMB
Bank 7
PLL 2
HSMA_CLKOUT_P[2]/N[2]
(LVDS)
HSMA_CLKOUT_P[1]/N[1]
(LVDS)
PLL 4
Bank 4
SMA
Chapter 2: Board Components
Clock Circuitry
Description
© October 2009 Altera Corporation