Altera Cyclone III LS Reference Manual page 50

2–42
Table 2–42
names and types are relative to the Cyclone III LS device in terms of I/O setting and
direction.
Table 2–42. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board Reference
U9.F6 Address valid
U9.B4 Chip enable
U9.E6 Clock
U9.F8 Output enable
U9.F7 Ready
U9.D4 Reset
U9.G8 Write enable
U9.C6 Address valid
U9.A1 Address bus
U9.B1 Address bus
U9.C1 Address bus
U9.D1 Address bus
U9.D2 Address bus
U9.A2 Address bus
U9.C2 Address bus
U9.A3 Address bus
U9.B3 Address bus
U9.C3 Address bus
U9.D3 Address bus
U9.C4 Address bus
U9.A5 Address bus
U9.B5 Address bus
U9.C5 Address bus
U9.D7 Address bus
U9.D8 Address bus
U9.A7 Address bus
U9.B7 Address bus
U9.C7 Address bus
U9.C8 Address bus
U9.A8 Address bus
U9.G1 Address bus
U9.H8 Address bus
U9.B6 Address bus (die select)
U9.F2 Data bus
U9.E2 Data bus
Cyclone III LS FPGA Development Board Reference Manual
lists the flash pin assignments, signal names, and functions. The signal
Description Schematic Signal Name
FLASH_ADVn
FLASH_CEn
FLASH_CLK
FLASH_OEn
FLASH_RDYBSYn
FLASH_RESETn
FLASH_WEn
FLASH_WPn
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
FSM_D0
FSM_D1
Chapter 2: Board Components
Cyclone III LS
Device
I/O Standard Pin Number
AF18
AH22
AH6
AD7
V4
AH5
AH17
—
AD14
AA17
AE12
AF21
AH2
AB12
AG24
AE25
AH21
2.5-V AD25
AC9
AF4
AE10
AH26
AG22
AF12
AE19
AA9
AE6
AG18
AE11
AB16
AE13
AG11
AE9
AH9
AH24
© October 2009 Altera Corporation
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