Altera Cyclone III LS Reference Manual page 36

2–28
Figure 2–8
PHY.
Figure 2–8. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
10/100/1000 Mbps
Ethernet MAC
Table 2–32
Table 2–32. Ethernet PHY Pin Assignments, Signal Names and Functions
Board Reference
U24.8 RGMII transmit clock
U24.23 Management bus interrupt
U24.25 Management bus control
U24.24 Management bus data
U24.28 Device reset
U24.2 RGMII receive clock
U24.94 RGMII receive control
U24.95 RGMII receive data
U24.92 RGMII receive data
U24.93 RGMII receive data
U24.91 RGMII receive data
U24.9 RGMII transmit control
U24.11 RGMII transmit data
U24.12 RGMII transmit data
U24.14 RGMII transmit data
U24.16 RGMII transmit data
Table 2–33
information.
Table 2–33. Ethernet PHY Component Reference and Manufacturing Information
Board
Reference Description
U24 Ethernet PHY BASE-T device
Cyclone III LS FPGA Development Board Reference Manual
shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111
RXD[3:0]
Marvell 88E1111
TXD[3:0]
PHY
Device
RGMII Interface
lists the Ethernet PHY interface pin assignments.
Description
lists the Ethernet PHY interface component reference and manufacturing
Manufacturer
Marvell Semiconductor
Transformer
Schematic Signal Name
ENET_GTX_CLK
ENET_INTn
ENET_MDC
ENET_MDIO
ENET_RESETn
ENET_RX_CLK
ENET_RX_DV
ENET_RXD0
ENET_RXD1
ENET_RXD2
ENET_RXD3
ENET_TX_EN
ENET_TXD0
ENET_TXD1
ENET_TXD2
ENET_TXD3
Manufacturing
Part Number
88E1111-B2-CAAIC000
Chapter 2: Board Components
Components and Interfaces
RJ45
Cyclone III LS
Device
I/O Standard Pin Number
AC14
N23
AH12
AH27
AF24
AG13
AH15
AF13
2.5-V
AB14
AH13
AG8
AF6
AE14
AD12
AB17
AC6
Manufacturer
Website
www.marvell.com
© October 2009 Altera Corporation