I/O Resources - Altera Cyclone III LS Reference Manual

Chapter 2: Board Components
Featured Device: Cyclone III LS Device
Table 2–3. Cyclone III LS Device Component Reference and Manufacturing Information
Board Reference
U15 FPGA, Cyclone III LS F780,
198K LEs, lead-free

I/O Resources

Figure 2–2
in the 780-pin FBGA package.
Figure 2–2. EP3CLS200 Device I/O Bank Diagram
Table 2–4
development board.
Table 2–4. Cyclone III LS Device Pin Count and Usage (Part 1 of 2)
Function
DDR2
MAX Bus
Flash, SSRAM, FSM Bus
HSMC Port A
HSMC Port B
Gigabit Ethernet
Buttons
Switches
LCD (1)
© October 2009 Altera Corporation
Description Manufacturer
Altera Corporation
illustrates the bank organization and I/O count for the EP3CLS200 device
B8
58 I/O
B1
47 I/O
B2
49 I/O
B3
59 I/O
lists the Cyclone III LS device pin count and usage by function on the
I/O Standard
1.8-V SSTL
2.5-V CMOS
2.5-V CMOS
2.5-V CMOS + LVDS
2.5-V CMOS
2.5-V CMOS
1.8-V / 2.5-V CMOS
1.8-V CMOS
2.5-V CMOS
Manufacturing
Part Number
EP3CLS200F780C7N
B7
59 I/O
B6
48 I/O
B5
52 I/O
B4
58 I/O
I/O Count
94 2 differential clocks, 4 DQS
8 —
82 —
84 34 LVDS, 2 differential clock inputs, 1
clock input
84 1 differential clock input, 1 clock input
16 1 clock input
5 1 DEV_CLRn
5 —
11 —
Cyclone III LS FPGA Development Board Reference Manual
2–5
Manufacturer
Website
www.altera.com
Special Pins