Altera Cyclone III LS Reference Manual page 11

Chapter 2: Board Components
Board Overview
Table 2–1. Cyclone III LS FPGA Development Board Components (Part 2 of 3)
Board Reference
D11 Load LED
D10 Error LED
D12 Factory LED
D29, D30, D31 Configuration select LEDs
D15, D16, D18, Ethernet LEDs
D20, D22
D2 HSMC port A present LED
D1 HSMC port B present LED
D3 Power LED
J18 LCD/HSMC Port B data select
J6 PS standard/fast select
S2 CPU reset push-button switch
S11 VCCA shutdown push-button
switch
S10 MAX II reset push-button
switch
S9 PGM select push-button
switch
S8 PGM configure push-button
switch
Clock Circuitry
U17 Programmable oscillator
(125 MHz default)
X3 66.6 MHz oscillator
X5 50 MHz oscillator
Y3 100 MHz oscillator
J7, J9 Clock FPGA input SMAs
J15 Clock FPGA output SMA
J13, J14 Clock output SMAs
General User Input/Output
D25, D26, D27, User LEDs
D28
S7 User DIP switch
© October 2009 Altera Corporation
Type
Illuminates when the MAX II CPLD EPM2210 System Controller is
actively configuring the FPGA.
Illuminates when the FPGA configuration from flash memory fails.
Illuminates when the factory image is loaded to the FPGA.
Illuminates to show the LED sequence that determines which flash
memory image loads to the FPGA when PGM SEL is pressed.
Shows the connection speed as well as transmit or receive activity.
Illuminates when a daughtercard is plugged into the HSMC port A.
Illuminates when a daughtercard is plugged into the HSMC port B.
Illuminates when 12-V power is present.
Controls data multiplexing to the FPGA from the LCD or
HSMB_D[65:75]. Placing a shunt on the jumper allows the FPGA to
control the LCD signals.
Placing a shunt sets the MSEL pins for passive serial standard
configuration. Otherwise, the MSEL pins is set for passive serial fast
configuration.
Press to reset the FPGA logic.
Turns VCCA power to the FPGA on and off. This switch initiates a
power-on reset.
Press to reset the MAX II CPLD EPM2210 System Controller.
Toggles the PGM LEDs which selects the program image that loads
from flash memory to the FPGA.
Configure the FGPA from flash memory based on the PGM LEDs
setting.
Programmable oscillator with a default frequency of 125.00 MHz. The
frequency is programmable using the MAX II CPLD EPM2210 System
Controller. For general use such as HSMC logic or gigabit Ethernet
(125 M/156.25 M)
66.6 MHz crystal oscillator for general purpose logic and DDR2
memory.
50 MHz crystal oscillator for general purpose logic.
100 MHz crystal oscillator for configuration purpose.
Drive LVPECL-compatible clock inputs into the clock multiplexer buffer
(U20).
Drive out 2.5-V CMOS clock output from the FPGA.
LVDS output clock from the clock multiplexer buffer (U20).
Four user LEDs. Illuminates when driven low.
Quad user DIP switches. When the switch is ON, a logic 0 is selected.
Description
Cyclone III LS FPGA Development Board Reference Manual
2–3