List Of Figures - Siemens Argus 7SR21 Technical Manual

List of Figures

Figure 1.5-1 Functional Diagram of 7SR21 Relay .............................................................................. 10
Figure 1.5-2 Connections Diagram for 7SR21 Relay ......................................................................... 11
Figure 1.5-3 Functional Diagram of 7SR22 Relay .............................................................................. 13
Figure 1.5-4 Connection Diagram for 7SR22 Relay ........................................................................... 14
Figure 2.5-1 7SR21 with 3 + 8 LEDs in E6 Case ............................................................................... 17
Figure 2.5-2 7SR220 with 3 + 16 LEDs in E8 Case ........................................................................... 17
Figure 2.5-3 7SR22 with Function Keys and 3 + 8 LEDs in E8 Case .................................................. 17
Figure 2.5-4 7SR22 with Function Keys & 3 + 8 LEDs in E8 Case and Ethernet
Communication Interface ............................................................................................... 18
Figure 2.8-1 Binary Input Logic.......................................................................................................... 21
Figure 2.9-1 Binary Output Logic ....................................................................................................... 22
Figure 2.11-1 Start-up Counter Meter ................................................................................................ 23
Figure 2.11-2 Start-up Counter Meter ................................................................................................ 23
Figure 2.11-3 Start-up Counter Meter Events .................................................................................... 24
Figure 3.1.1-1 Logic Diagram: Directional Overcurrent Element (67) ............................................. 26
Figure 3.1.2-1 Logic Diagram: Instantaneous Over-current Element .............................................. 27
Figure 3.1.3-1 Logic Diagram: Time Delayed Overcurrent Element ............................................... 29
Figure 3.2-1 Logic Diagram: Voltage Controlled Overcurrent Protection............................................. 30
Figure 3.3.1-1 Logic Diagram: Derived Directional Earth Fault Element ......................................... 32
Figure 3.3.2-1 Logic Diagram: Derived Instantaneous Earth Fault Element ................................... 33
Figure 3.3.3-1 Logic Diagram: Derived Time Delayed Earth Fault Protection ................................. 34
Figure 3.4.1-1 Logic Diagram: Measured Directional Earth Fault Protection .................................. 35
Figure 3.4.2-1 Logic Diagram: Measured Instantaneous Earth-fault Element ................................. 36
Figure 3.4.3-1 Logic Diagram: Measured Time Delayed Earth Fault Element (51G) ...................... 37
Figure 3.5.1-1 Logic Diagram: SEF Directional Element (67SEF) .................................................. 39
Figure 3.5.2-1 Logic Diagram: 50 SEF Instantaneous Element...................................................... 40
Figure 3.5.2-2 Logic Diagram: 50 SEF Instantaneous Element Compensated Networks................ 40
Figure 3.5.3-1 Logic Diagram: 51 SEF Time Delayed Element ...................................................... 42
Figure 3.5.3-2 Logic Diagram: 51 SEF Time Delayed Element Compensated Networks ................ 42
Figure 3.6-1 Logic Diagram: High Impedance REF (64H) .................................................................. 43
Figure 3.7-1 Logic Diagram: Cold Load Settings (51c) ....................................................................... 44
Figure 3.8-1 Logic Diagram: Negative Phase Sequence Overcurrent (46NPS) .................................. 45
Figure 3.9-1 Logic Diagram: Undercurrent Detector (37, 37G & 37SEF) ............................................ 46
Figure 3.10-1 Logic Diagram: Undercurrent Guarded Detector (37) .............................................. 46
Figure 3.11-1 Logic Diagram: Thermal Overload Protection (49S) ................................................ 48
Figure 3.12-1 Logic Diagram: Arc Flash Detector (50 AFD) .......................................................... 49
Figure 3.13-1 Logic Diagram: Under/Over Voltage Elements (27/59) ........................................... 50
Figure 3.14-1 Logic Diagram: NPS Overvoltage Protection (47) ................................................... 51
Figure 3.15-1 Logic Diagram: Neutral Overvoltage Element ......................................................... 52
Figure 3.16-1 Logic Diagram: Under/Over Frequency Detector (81) ............................................. 53
Figure 3.17-1 Logic Diagram: Power Protection (32) .................................................................... 54
Figure 3.18-1 Logic Diagram: Sensitive Power Protection (32S) ................................................... 55
Figure 3.19-1 Logic Diagram: Power Factor Protection (55) ......................................................... 56
Figure 4.1.2-1 Typical Sequence with 3 Instantaneous and 1 Delayed trip .................................... 59
Figure 4.7-1 Basic Auto-Reclose Sequence Diagram ........................................................................ 64
Figure 4.9.3-1 Voltage Detector Operation .................................................................................... 67
Figure 4.9.4-1 Check Sync Function ............................................................................................. 68
Figure 4.9.7-1 System Sync Function ........................................................................................... 70
Figure 4.9.8-1 Close On Zero Function ......................................................................................... 71
Figure 4.9.8-2 Close On Zero Timing ............................................................................................ 71
Figure 4.10-1 Voltage Detector Operation .................................................................................... 72
Figure 4.11-1 Logic Diagram: Circuit Breaker Status .................................................................... 73
Figure 4.12-1Sequence Diagram: Quick Logic PU/DO Timers (Counter Reset Mode Off) .................. 76
Figure 5.1-1 Logic Diagram: Circuit Breaker Fail Protection (50BF) ................................................... 77
Figure 5.2-1 Logic Diagram: VT Supervision Function (60VTS) ......................................................... 79
Figure 5.4.1-1 Logic Diagram: CT Supervision Function (60CTS-I) - 7SR21 & 7SR22 .................. 80
Figure 5.4.2-1 Logic Diagram: CT Supervision Function (60CTS) - 7SR22 ................................... 80
Figure 5.5-1 Logic Diagram: Broken Conductor Function (46BC) ....................................................... 81
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7SR210 & 7SR220 Description of Operation
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