Gem3 Ethernet (Mio 64-77) - Xilinx ZCU111 User Manual

X-Ref Target - Figure 3-9
The connections between the USB 2.0 PHY (U12) and the XCZU28DR RFSoC PS bank 502 are
referenced in Appendix B, Xilinx Design

GEM3 Ethernet (MIO 64-77)

The PS-side Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet
interface (see Figure
before being routed to an RJ45 Ethernet connector. The RGMII Ethernet PHY is boot
strapped to PHY address 5'b01100 (0x0C) and Auto Negotiation is set to Enable. The
communication with the device is described in the DP83867 RGMII PHY data sheet
X-Ref Target - Figure 3-10
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
Figure 3-9: USB3320 ULPI Transceiver Circuit
Constraints.
3-10), which connects to a TI DP83867IRPAP Ethernet RGMII PHY
RGMII
GEM
MIO
MDIO
Figure 3-10: Ethernet Block Diagram
www.xilinx.com
Chapter 3: Board Component Descriptions
RJ45 and
TI
Magnetics
DP83867IR
X20534-062118
X20484-062118
[Ref 20].
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